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  • 454ce519a5 Updated the figure showing the layout of an instruction. main glm94 2025-03-10 00:49:51 -05:00
  • 4f155090f3 Updated the opcode tables. glm94 2025-02-28 00:54:05 -06:00
  • 043311b2e0 Added a section about the Option byte. Garritt McCune 2025-02-27 16:37:22 -06:00
  • dac37cb167 Added a bit more to the instruction listing start in section 2.2. Need to update the text to talk about offsets in the options byte. glm94 2025-02-26 01:52:46 -06:00
  • 1d063f7bba Refactored the section about the ISA. Garritt McCune 2025-02-25 16:35:46 -06:00
  • 9393a84f96 Cleaned up the code a bit and updated Figure 2.1 to show the physical layout of an instruction. Added some text in Section 2.1. Garritt McCune 2025-02-24 16:34:19 -06:00
  • 57a469c153 Added commands to build op code tables for instructions with one or no parameters. Garritt McCune 2025-02-24 09:39:34 -06:00
  • 3680d24d68 Removed invalid Option nibble codes and refactored most of the instructions' section code to use the new command. glm94 2025-02-24 02:01:41 -06:00
  • 02b3c9185d Updated the way I build the opcode table to be a little less repetitive. Now instead of making it an environment it is now a command that will build the arguments based on the 'Options' bit hexcode. glm94 2025-02-24 01:14:30 -06:00
  • 5068c6c293 Added a new environment for creating the opcode tables. hoping this will simplify the setup and make things easier to maintain. Garritt McCune 2025-02-20 13:50:59 -06:00
  • e8d1501d75 Updated the text that introduces the ISA. Garritt McCune 2025-02-18 16:13:40 -06:00
  • 53962331d5 Updated the text around Memory and added a section for the firmware / initialization. Garritt McCune 2025-02-07 16:08:41 -06:00
  • 883c48270f Started brainstorming the memory map. Garritt McCune 2025-02-06 16:13:29 -06:00
  • 43b8dd0119 Added a conventions and data types section. glm94 2025-02-05 00:42:15 -06:00
  • 7baadf96fa Added a section to the memory map for the video memory. Garritt McCune 2025-02-04 16:23:50 -06:00
  • eba9778993 Created a basic setup for the figure for the memory layout / map. Garritt McCune 2025-02-04 15:17:13 -06:00
  • 472b9f839f Added a bit about the flags register glm94 2025-02-03 23:48:30 -06:00
  • d3ccd6678c Added some information about the memory layout and a figure for the bit ordering in the registers. glm94 2025-02-03 23:12:00 -06:00
  • f85a74bd83 Updated chapter 1 to be more fleshed out. glm94 2025-02-02 00:15:44 -06:00
  • 05adb3d0c9 Added a few more instructions. glm94 2024-09-10 23:29:43 -05:00
  • 892e34af93 Fleshed out and updated all the current instructions' opcodes, arguments and functions. glm94 2024-09-03 23:21:14 -05:00
  • b14779c612 Updated some of the tables to reflect the new encoding scheme. Cleared out some of the old defines and the MOV table so the code can compile. Will fix up the rest of the instructions in a future commit. Garritt McCune 2024-09-03 16:36:16 -05:00
  • abbe9828e9 Updated the way the encoding for the 'mode' byte works. glm94 2024-09-01 14:51:25 -05:00
  • cc4a220aed Started to work on how the MOV instruction will work / what modes it will support. Garritt McCune 2024-08-22 16:37:55 -05:00
  • efb8bf8883 Further refined some details about how ADD will work which will impact the way the rest of the processor will behave. Garritt McCune 2024-08-22 14:23:04 -05:00
  • c72b77ca19 Started to flesh out the opcodes but am having issues with Tex packaging trying to get the xint package for hopefully converting bit patterns to a hex code. Garritt McCune 2024-08-21 15:38:42 -05:00
  • c8ff04050e Updated the look of references Garritt McCune 2024-08-20 16:34:35 -05:00
  • e2e78a88fd Started the section on the supported interrupts just to get a few thoughts down. glm94 2024-08-19 19:21:49 -05:00
  • 47f2f633c5 Updated the encoding figure to show the layout of the instructions, also decided that the mode byte will not be required for instructions with no arguments, but need to update the text to reflect this still. Garritt McCune 2024-08-09 15:09:43 -05:00
  • 8c0de609b5 Updated the description about the ISA's encoding scheme since it is no longer fixed width. Garritt McCune 2024-08-08 15:44:15 -05:00
  • 3f78a00be8 Updated the way the mode setting works by allocating an entire byte for it. Garritt McCune 2024-08-07 16:52:28 -05:00
  • b31c1fbe76 Started on a new figure to explain a new instruction layout, no more fixed length encoding, basically. glm94 2024-08-01 23:22:35 -05:00
  • 5cd831aeb9 Added some more instructions to help flesh out the ISA section. Garritt McCune 2024-07-31 15:33:25 -05:00
  • 04a06fc2ff Tweaked the figures a bit more. Garritt McCune 2024-07-24 16:27:52 -05:00
  • 4acb5a7625 Updated the register and memory layout figure. Garritt McCune 2024-07-23 14:52:56 -05:00
  • 1b9910e908 Started to mess around with setting up the figure for the layout of the registers and main memory. Garritt McCune 2024-07-22 16:09:00 -05:00
  • b1e3e585f4 Minor tweaks and added a note or two. Garritt McCune 2024-07-19 16:26:21 -05:00
  • 8003d389e9 Updated the encoding layout figures. Garritt McCune 2024-07-19 15:54:34 -05:00
  • df15bb60e7 Updated the Encoding Scheme section adding a 'operand mode' setting to the encoding as well changing the placement of the figures in that section. Garritt McCune 2024-07-19 13:50:44 -05:00
  • 5c646a4835 First opcode table setup. glm94 2024-07-19 00:53:29 -05:00
  • b6b340fd62 Updated the figure for instruction encoding, mostly just example code for more proper figures. glm94 2024-07-18 00:24:44 -05:00
  • 51c79d74aa Added the start of a second chapter for the ISA itself. glm94 2024-07-15 23:57:27 -05:00
  • 70849bb698 Added a little more about the registers and tweaked the code for the register bit layout figure. glm94 2024-06-16 01:38:41 -05:00
  • dcdf266cdd Initial commit and setup. glm94 2024-05-09 20:31:43 -05:00