Updated some of the tables to reflect the new encoding scheme. Cleared out some of the old defines and the MOV table so the code can compile. Will fix up the rest of the instructions in a future commit.
This commit is contained in:
Garritt McCune
+45
-64
@@ -23,9 +23,9 @@ Instructions are variable width with most instructions' width being determined b
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\draw (-8, 4) node[above] {7} rectangle (-6, 3) node[above = 1] {0};
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\node at (-7, 2.5) {Opcode};
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\draw (-5, 4) node[above] {7} rectangle (-3, 3) node[above = 1] {0};
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\draw[dashed] (-4.5, 3) -- (-4.5, 4) node[above] {5};
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\draw[dashed] (-4.5, 3) -- (-4.5, 4) node[above] {6};
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\draw[dashed] (-4, 3) -- (-4, 4) node[above] {4};
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\draw[dashed] (-3.5, 3) -- (-3.5, 4) node[above] {1};
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\draw[dashed] (-3.5, 3) -- (-3.5, 4) node[above] {2};
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\node at (-4, 2.5) {Mode};
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\node (A) at (-4, 2.0) {(If required)};
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@@ -60,36 +60,35 @@ Instructions are variable width with most instructions' width being determined b
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\end{tikzpicture}
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\caption{Encoding}
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\label{fig:opencoding} % https://www.overleaf.com/learn/latex/Referencing_Figures
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%\paragraph{Note} Figure \ref{fig:ModeSettingEncodingFigure} shows the options for the \textit{Mode} byte.
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\end{figure}
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\def\registerType{00}\def\registerValueType{01}
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\def\immediateType{10}\def\addressType{11}
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\def\noWidth{00}\def\eightBitWidth{01}\def\sixteenBitWidth{10}\def\thirtyBitWidth{11}
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\def\registerBit{0}\def\registerBitA{8}
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\def\eightBit{1}\def\eightBitA{9}
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\def\sixteenBit{2}\def\sixteenBitA{A}
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\def\thirtyBit{4}\def\thirtyBitA{C}
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\def\none{F}
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%Argument options
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% Register first
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\newcommand{\rRArgH}{0}\newcommand{\rRaArgH}{1}\newcommand{\rAArgH}{3}
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% Register contains address first
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\newcommand{\raRArgH}{4}\newcommand{\raRaArgH}{5}\newcommand{\raAArgH}{7}
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% Immediate first
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\newcommand{\immRArgH}{8}\newcommand{\immRaArgH}{9}\newcommand{\immAArgH}{B}
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% Address first
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\newcommand{\aRArgH}{C}\newcommand{\aRaArgH}{D}\newcommand{\aAArgH}{F}
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%Width hex codes
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\newcommand{\byteWidthH}{1}\newcommand{\shortWidthH}{2}\newcommand{\intWidthH}{3}
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\begin{figure}
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\begin{tabularx}{\textwidth}{ | c | c | X | }
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\hline
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Type & Pattern & Description \\
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\hline
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Register & \registerType & Operand is a register \\
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\&Register & \registerValueType & Operand is a 32-bit address stored in a register \\
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Immediate & \immediateType & Operand is an 8-, 16- or 32-bit value \\
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Address & \addressType & Operand is a 32-bit address \\
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Register & 00 & Operand is a register \\
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\&Register & 01 & Operand is a 32-bit address stored in a register \\
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Immediate & 10 & Operand is an 8-, 16- or 32-bit value \\
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Address & 11 & Operand is a 32-bit address \\
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\hline
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\multicolumn{3}{ | X | }{Source Operand Width Patterns} \\
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\hline
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Invalid & \noWidth & Source must have a width \\
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8-bit & \eightBitWidth & 8-bit wide source \\
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16-bit & \sixteenBitWidth & 16-bit wide source \\
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32-bit & \thirtyBitWidth & 32-bit wide source \\
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Invalid & 00 & Source must have a width \\
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8-bit & 01 & 8-bit wide source \\
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16-bit & 10 & 16-bit wide source \\
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32-bit & 11 & 32-bit wide source \\
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\hline
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\end{tabularx}
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\caption{Operand Type and Width Bit Patterns}
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@@ -103,10 +102,12 @@ The /r represents a byte that specifies a register. /immX is for the immediate d
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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01 \registerBit\registerBit & add /r, /r & /r & /r \\
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01 \eightBit\registerBit & add /imm8, /r & /imm8 & /r \\
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01 \sixteenBit\registerBit & add /imm16, /r & /imm16 & /r \\
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01 \thirtyBit\registerBit & add /imm32, /r & /imm32 & /r \\
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01 \rRArgH\byteWidthH & add byte /r, /r & /r & /r \\
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01 \rRArgH\shortWidthH & add short /r, /r & /r & /r \\
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01 \rRArgH\intWidthH & add (int) /r, /r & /r & /r \\
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01 \immRArgH\byteWidthH & add byte /imm8, /r & /imm8 & /r \\
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01 \immRArgH\shortWidthH & add short /imm16, /r & /imm16 & /r \\
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01 \immRArgH\intWidthH & add (int) /imm32, /r & /imm32 & /r \\
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\hline
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\end{tabularx}
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\paragraph{Description} Adds two unsigned values together, the source (operand one) and the destination (operand two), storing the result in destination. The overflow flag (OF) is set if the result is less than the source and the zero flag (ZF) is set when the result of addition is zero.
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@@ -116,10 +117,12 @@ The /r represents a byte that specifies a register. /immX is for the immediate d
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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02 \registerBit\registerBit & sub /r, /r & /r & /r \\
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02 \eightBit\registerBit & sub /imm8, /r & /imm8 & /r \\
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02 \sixteenBit\registerBit & sub /imm16, /r & /imm16 & /r \\
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02 \thirtyBit\registerBit & sub /imm32, /r & /imm32 & /r \\
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02 \rRArgH\byteWidthH & sub byte /r, /r & /r & /r \\
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02 \rRArgH\shortWidthH & sub short /r, /r & /r & /r \\
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02 \rRArgH\intWidthH & sub (int) /r, /r & /r & /r \\
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02 \immRArgH\byteWidthH & sub byte /imm8, /r & /imm8 & /r \\
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02 \immRArgH\shortWidthH & sub short /imm16, /r & /imm16 & /r \\
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02 \immRArgH\intWidthH & sub (int) /imm32, /r & /imm32 & /r \\
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\hline
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\end{tabularx}
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\paragraph{Description} Subtracts two unsigned values, the source (operand one) and the destination (operand two), storing the result in destination. The underflow flag (UF) is set if the result is greater than the source and the zero flag (ZF) is set when the result of subtraction is zero.
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@@ -129,10 +132,12 @@ The /r represents a byte that specifies a register. /immX is for the immediate d
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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03 \registerBit\registerBit & mul /r, /r & /r & /r \\
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03 \eightBit\registerBit & mul /imm8, /r & /imm8 & /r \\
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03 \sixteenBit\registerBit & mul /imm16, /r & /imm16 & /r \\
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03 \thirtyBit\registerBit & mul /imm32, /r & /imm32 & /r \\
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03 \rRArgH\byteWidthH & mul byte /r, /r & /r & /r \\
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03 \rRArgH\shortWidthH & mul short /r, /r & /r & /r \\
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03 \rRArgH\intWidthH & mul (int) /r, /r & /r & /r \\
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03 \immRArgH\byteWidthH & mul byte /imm8, /r & /imm8 & /r \\
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03 \immRArgH\shortWidthH & mul short /imm16, /r & /imm16 & /r \\
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03 \immRArgH\intWidthH & mul (int) /imm32, /r & /imm32 & /r \\
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\hline
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\end{tabularx}
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\paragraph{Description} Multiplies two unsigned values together, the source (operand one) and the destination (operand two), storing the result in destination. The overflow flag (OF) is set if the result is less than the source and the zero flag (ZF) is set when the result of addition is zero.
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@@ -142,10 +147,12 @@ The /r represents a byte that specifies a register. /immX is for the immediate d
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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04 \registerBit\registerBit & div /r, /r & /r & /r \\
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04 \eightBit\registerBit & div /imm8, /r & /imm8 & /r \\
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04 \sixteenBit\registerBit & div /imm16, /r & /imm16 & /r \\
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04 \thirtyBit\registerBit & div /imm32, /r & /imm32 & /r \\
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04 \rRArgH\byteWidthH & div byte /r, /r & /r & /r \\
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04 \rRArgH\shortWidthH & div short /r, /r & /r & /r \\
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04 \rRArgH\intWidthH & div (int) /r, /r & /r & /r \\
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04 \immRArgH\byteWidthH & div byte /imm8, /r & /imm8 & /r \\
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04 \immRArgH\shortWidthH & div short /imm16, /r & /imm16 & /r \\
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04 \immRArgH\intWidthH & div (int) /imm32, /r & /imm32 & /r \\
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\hline
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\end{tabularx}
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\paragraph{Description} Divides two unsigned values, the source (operand one) and the destination (operand two), storing the result in destination. The underflow flag (UF) is set if the result is greater than the source and the zero flag (ZF) is set when the result of subtraction is zero.
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@@ -155,32 +162,6 @@ The /r represents a byte that specifies a register. /immX is for the immediate d
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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05 \registerBit\registerBit & mov /r, /r & /r & /r \\
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05 \registerBit\eightBitA & mov byte /r, /addr & /r & /addr \\
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05 \registerBit\sixteenBitA & mov short /r, /addr & /r & /addr \\
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05 \registerBit\thirtyBitA & mov (int) /r, /addr & /r & /addr \\
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05 \registerBitA\registerBit & mov [/r], /r & [/r] & /r \\
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05 \registerBitA\registerBitA & mov (int) [/r], [/r] & [/r] & [/r] \\
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05 \registerBitA\eightBitA & mov byte [/r], /addr & [/r] & /addr \\
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05 \registerBitA\sixteenBitA & mov short [/r], /addr & [/r] & /addr \\
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05 \registerBitA\thirtyBitA & mov (int) [/r], /addr & [/r] & /addr \\
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05 \eightBitA\registerBit & mov byte /addr, /r & /addr & /r \\
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05 \sixteenBitA\registerBit & mov short /addr, /r & /addr & /r \\
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05 \thirtyBitA\registerBit & mov (int) /addr, /r & /addr & /r \\
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05 \eightBit\registerBit & mov byte /imm8, /r & /imm8 & /r \\
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05 \eightBit\registerBitA & mov byte /imm8, [/r] & /imm8 & [/r] \\
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05 \eightBit\eightBitA & mov byte /imm8, /addr & /imm8 & /addr \\
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05 \sixteenBit\registerBit & mov short /imm16, /r & /imm16 & /r \\
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05 \sixteenBit\registerBitA & mov short /imm16, [/r] & /imm16 & [/r] \\
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05 \sixteenBit\sixteenBitA & mov short /imm16, /addr & /imm16 & /addr \\
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05 \thirtyBit\registerBit & mov (int) /imm32, /r & /imm32 & /r \\
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05 \thirtyBit\registerBitA & mov (int) /imm32, [/r] & /imm32 & [/r] \\
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05 \thirtyBit\thirtyBitA & mov (int) /imm32, /addr & /imm32 & /addr \\
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\hline
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\end{tabularx}
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\paragraph{Description} Copies the source (operand one) value to the destination (operand two).
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