Started to work on how the MOV instruction will work / what modes it will support.
This commit is contained in:
Garritt McCune
+78
-10
@@ -75,28 +75,96 @@ Instructions are variable width with their total length being determined by the
|
||||
\end{figure}
|
||||
\clearpage
|
||||
\section{Instructions}
|
||||
The /r represents a byte that specifies a register. /iX is for the immediate data type, where \textit{X} defines the width, which are 8, 16, or 32 bits.
|
||||
The /r represents a byte that specifies a register. /immX is for the immediate data type, where \textit{X} defines the width, which are 8, 16, or 32 bits. An address is defined as /addrX with the \textit{X} denoting the size of the data that will be written which can be 8, 16 or 32 bits, with the address itself always being 32-bits wide.
|
||||
\subsection{Add}
|
||||
\begin{tabularx}{\textwidth}{ | X | X | c | c | }
|
||||
\begin{tabularx}{\textwidth}{ | c | X | c | c | }
|
||||
\hline
|
||||
Opcode & Instruction & Operand One & Operand Two \\
|
||||
\hline
|
||||
01 \registerBit\registerBit & add /r, /r & /r & /r \\
|
||||
01 \eightBit\registerBit & add /i8, /r & /i8 & /r \\
|
||||
01 \sixteenBit\registerBit & add /i16, /r & /i16 & /r \\
|
||||
01 \thirtyBit\registerBit & add /i32, /r & /i32 & /r \\
|
||||
01 \eightBit\registerBit & add /imm8, /r & /imm8 & /r \\
|
||||
01 \sixteenBit\registerBit & add /imm16, /r & /imm16 & /r \\
|
||||
01 \thirtyBit\registerBit & add /imm32, /r & /imm32 & /r \\
|
||||
\hline
|
||||
\end{tabularx}
|
||||
\paragraph{Description} Adds two unsigned values together; the source (operand one) and the destination (operand two) with the result stored in destination. The overflow flag (OF) is set if the result is less than the source and the zero flag (ZF) is set when the result of addition is zero.
|
||||
\paragraph{Description} Adds two unsigned values together, the source (operand one) and the destination (operand two), storing the result in destination. The overflow flag (OF) is set if the result is less than the source and the zero flag (ZF) is set when the result of addition is zero.
|
||||
\paragraph{Flags Affected} OF and ZF.
|
||||
\subsection{Sub}
|
||||
\OpcodeTable{01 /r /r}{sub /r, /r}{Register}{Register}{Subtracts \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
|
||||
\begin{tabularx}{\textwidth}{ | c | X | c | c | }
|
||||
\hline
|
||||
Opcode & Instruction & Operand One & Operand Two \\
|
||||
\hline
|
||||
02 \registerBit\registerBit & sub /r, /r & /r & /r \\
|
||||
02 \eightBit\registerBit & sub /imm8, /r & /imm8 & /r \\
|
||||
02 \sixteenBit\registerBit & sub /imm16, /r & /imm16 & /r \\
|
||||
02 \thirtyBit\registerBit & sub /imm32, /r & /imm32 & /r \\
|
||||
\hline
|
||||
\end{tabularx}
|
||||
\paragraph{Description} Subtracts two unsigned values, the source (operand one) and the destination (operand two), storing the result in destination. The underflow flag (UF) is set if the result is greater than the source and the zero flag (ZF) is set when the result of subtraction is zero.
|
||||
\paragraph{Flags Affected} UF and ZF.
|
||||
\subsection{Mul}
|
||||
\OpcodeTable{01 /r /r}{mul /r, /r}{Register}{Register}{Multiplies \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
|
||||
\begin{tabularx}{\textwidth}{ | c | X | c | c | }
|
||||
\hline
|
||||
Opcode & Instruction & Operand One & Operand Two \\
|
||||
\hline
|
||||
03 \registerBit\registerBit & mul /r, /r & /r & /r \\
|
||||
03 \eightBit\registerBit & mul /imm8, /r & /imm8 & /r \\
|
||||
03 \sixteenBit\registerBit & mul /imm16, /r & /imm16 & /r \\
|
||||
03 \thirtyBit\registerBit & mul /imm32, /r & /imm32 & /r \\
|
||||
\hline
|
||||
\end{tabularx}
|
||||
\paragraph{Description} Multiplies two unsigned values together, the source (operand one) and the destination (operand two), storing the result in destination. The overflow flag (OF) is set if the result is less than the source and the zero flag (ZF) is set when the result of addition is zero.
|
||||
\paragraph{Flags Affected} OF and ZF.
|
||||
\subsection{Div}
|
||||
\OpcodeTable{01 /r /r}{div /r, /r}{Register}{Register}{Divides \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
|
||||
\begin{tabularx}{\textwidth}{ | c | X | c | c | }
|
||||
\hline
|
||||
Opcode & Instruction & Operand One & Operand Two \\
|
||||
\hline
|
||||
04 \registerBit\registerBit & div /r, /r & /r & /r \\
|
||||
04 \eightBit\registerBit & div /imm8, /r & /imm8 & /r \\
|
||||
04 \sixteenBit\registerBit & div /imm16, /r & /imm16 & /r \\
|
||||
04 \thirtyBit\registerBit & div /imm32, /r & /imm32 & /r \\
|
||||
\hline
|
||||
\end{tabularx}
|
||||
\paragraph{Description} Divides two unsigned values, the source (operand one) and the destination (operand two), storing the result in destination. The underflow flag (UF) is set if the result is greater than the source and the zero flag (ZF) is set when the result of subtraction is zero.
|
||||
\paragraph{Flags Affected} UF and ZF.
|
||||
\subsection{Mov}
|
||||
\OpcodeTable{04 /mod /r /r}{mov /mod /r, /r}{Register}{Register}{Copies the 32-bit value from \textit{Operand 2} to \textit{Operand 1}.}
|
||||
\begin{tabularx}{\textwidth}{ | c | X | c | c | }
|
||||
\hline
|
||||
Opcode & Instruction & Operand One & Operand Two \\
|
||||
\hline
|
||||
05 \registerBit\registerBit & mov /r, /r & /r & /r \\
|
||||
05 \registerBit\eightBitA & mov /r, /addr8 & /r & /addr8 \\
|
||||
05 \registerBit\sixteenBitA & mov /r, /addr16 & /r & /addr16 \\
|
||||
05 \registerBit\thirtyBitA & mov /r, /addr32 & /r & /addr32 \\
|
||||
|
||||
05 \registerBitA\registerBit & mov [/r], /r & [/r] & /r \\
|
||||
05 \registerBitA\eightBitA & mov [/r], /addr8 & [/r] & /addr8 \\
|
||||
05 \registerBitA\sixteenBitA & mov [/r], /addr16 & [/r] & /addr16 \\
|
||||
05 \registerBitA\thirtyBitA & mov [/r], /addr32 & [/r] & /addr32 \\
|
||||
|
||||
05 \eightBitA\registerBit & mov /addr8, /r & /addr8 & /r \\
|
||||
05 \sixteenBitA\registerBit & mov /addr16, /r & /addr16 & /r \\
|
||||
05 \thirtyBitA\registerBit & mov /addr32, /r & /addr32 & /r \\
|
||||
|
||||
05 \eightBit\registerBit & mov /imm8, /r & /imm8 & /r \\
|
||||
05 \eightBit\registerBitA & mov /imm8, [/r] & /imm8 & [/r] \\
|
||||
05 \eightBit\eightBitA & mov /imm8, /addr8 & /imm8 & /addr8 \\
|
||||
05 \eightBit\sixteenBitA & mov /imm8, /addr16 & /imm8 & /addr16 \\
|
||||
05 \eightBit\thirtyBitA & mov /imm8, /addr32 & /imm8 & /addr32 \\
|
||||
|
||||
05 \sixteenBit\registerBit & mov /imm16, /r & /imm16 & /r \\
|
||||
05 \sixteenBit\registerBitA & mov /imm16, [/r] & /imm16 & [/r] \\
|
||||
05 \sixteenBit\sixteenBitA & mov /imm16, /addr16 & /imm16 & /addr16 \\
|
||||
05 \sixteenBit\thirtyBitA & mov /imm16, /addr32 & /imm16 & /addr32 \\
|
||||
|
||||
05 \thirtyBit\registerBit & mov /imm32, /r & /imm32 & /r \\
|
||||
05 \thirtyBit\registerBitA & mov /imm32, [/r] & /imm32 & [/r] \\
|
||||
05 \thirtyBit\thirtyBitA & mov /imm32, /addr32 & /imm32 & /addr32 \\
|
||||
\hline
|
||||
\end{tabularx}
|
||||
\paragraph{Description} Copies the source (operand one) value to the destination (operand two).
|
||||
\paragraph{Flags Affected} None.
|
||||
\subsection{AND}
|
||||
\OpcodeTable{01 /r /r}{and /r, /r}{Register}{Register}{Bit-wise ANDs \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
|
||||
\subsection{OR}
|
||||
|
||||
Reference in New Issue
Block a user