Fleshed out and updated all the current instructions' opcodes, arguments and functions.
This commit is contained in:
+231
-38
@@ -1,19 +1,6 @@
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\chapter{Instruction Set Architecture}
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Instructions are variable width with most instructions' width being determined by the \textit{mode} byte that follows immediately after the opcode byte. The \textit{mode} byte is split into four parts, with the upper nibble describing what the types of source and destination operands the instruction is to deal with. Following those four bits is two reserved bits and finally the final two bits in the least significant half of the lower nibble, the \textit{source width}. Depending on the \textit{source type} bits, the next number of bytes to be read for the source operand can be 8-, 16- or 32-bits and the same applies to the \textit{destination type} bits. A more visual layout of this may be found in Figure \ref{fig:opencoding}.
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\newcommand{\OpcodeTable}[5] {
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\noindent
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\begin{minipage}{\textwidth}
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\begin{tabularx}{\textwidth}{ | X | X | X | X | }
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\hline
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Opcode Hex & Instruction & Operand 1 & Operand 2 \\
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\hline
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#1 & #2 & #3 & #4 \\
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\hline
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\end{tabularx}
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\paragraph{Description} #5
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\end{minipage}
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}
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\section{Instruction Layout}
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% Placement info here: https://en.wikibooks.org/wiki/LaTeX/Floats,_Figures_and_Captions#Figures
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% Paths: https://tikz.dev/tikz-paths
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@@ -79,9 +66,9 @@ Instructions are variable width with most instructions' width being determined b
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Type & Pattern & Description \\
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\hline
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Register & 00 & Operand is a register \\
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\&Register & 01 & Operand is a 32-bit address stored in a register \\
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{[Register]} & 01 & Operand is a 32-bit address stored in a register \\
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Immediate & 10 & Operand is an 8-, 16- or 32-bit value \\
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Address & 11 & Operand is a 32-bit address \\
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{[Immediate]} & 11 & Operand is treated as a 32-bit address \\
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\hline
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\multicolumn{3}{ | X | }{Source Operand Width Patterns} \\
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\hline
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@@ -162,50 +149,256 @@ The /r represents a byte that specifies a register. /immX is for the immediate d
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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05 \rRArgH\byteWidthH & mov byte /r, /r & /r & /r \\
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05 \rRArgH\shortWidthH & mov short /r, /r & /r & /r \\
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05 \rRArgH\intWidthH & mov (int) /r, /r & /r & /r \\
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05 \rRaArgH\byteWidthH & mov byte /r, [/r] & /r & [/r] \\
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05 \rRaArgH\shortWidthH & mov short /r, [/r] & /r & [/r] \\
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05 \rRaArgH\intWidthH & mov (int) /r, [/r] & /r & [/r] \\
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05 \rAArgH\byteWidthH & mov byte /r, [imm32] & /r & [imm32] \\
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05 \rAArgH\shortWidthH & mov short /r, [imm32] & /r & [imm32] \\
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05 \rAArgH\intWidthH & mov (int) /r, [imm32] & /r & [imm32] \\
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05 \raRArgH\byteWidthH & mov byte [/r], /r & [/r] & /r \\
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05 \raRArgH\shortWidthH & mov short [/r], /r & [/r] & /r \\
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05 \raRArgH\intWidthH & mov (int) [/r], /r & [/r] & /r \\
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05 \raRaArgH\byteWidthH & mov byte [/r], [/r] & [/r] & [/r] \\
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05 \raRaArgH\shortWidthH & mov short [/r], [/r] & [/r] & [/r] \\
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05 \raRaArgH\intWidthH & mov (int) [/r], [/r] & [/r] & [/r] \\
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05 \raAArgH\byteWidthH & mov byte [/r], [imm32] & [/r] & [imm32] \\
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05 \raAArgH\shortWidthH & mov short [/r], [imm32] & [/r] & [imm32] \\
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05 \raAArgH\intWidthH & mov (int) [/r], [imm32] & [/r] & [imm32] \\
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05 \immRArgH\byteWidthH & mov byte imm8, /r & imm8 & /r \\
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05 \immRArgH\shortWidthH & mov short imm16, /r & imm16 & /r \\
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05 \immRArgH\intWidthH & mov (int) imm32, /r & imm32 & /r \\
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05 \immRaArgH\byteWidthH & mov byte imm8, [/r] & imm8 & [/r] \\
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05 \immRaArgH\shortWidthH & mov short imm16, [/r] & imm16 & [/r] \\
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05 \immRaArgH\intWidthH & mov (int) imm32, [/r] & imm32 & [/r] \\
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05 \immAArgH\byteWidthH & mov byte imm8, [imm32] & imm8 & [imm32] \\
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05 \immAArgH\shortWidthH & mov short imm16, [imm32] & imm16 & [imm32] \\
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05 \immAArgH\intWidthH & mov (int) imm32, [imm32] & imm32 & [imm32] \\
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05 \aRArgH\byteWidthH & mov byte [imm32], /r & [imm32] & /r \\
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05 \aRArgH\shortWidthH & mov short [imm32], /r & [imm32] & /r \\
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05 \aRArgH\intWidthH & mov (int) [imm32], /r & [imm32] & /r \\
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05 \aRaArgH\byteWidthH & mov byte [imm32], [/r] & [imm32] & [/r] \\
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05 \aRaArgH\shortWidthH & mov short [imm32], [/r] & [imm32] & [/r] \\
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05 \aRaArgH\intWidthH & mov (int) [imm32], [/r] & [imm32] & [/r] \\
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05 \aAArgH\byteWidthH & mov byte [imm32], [imm32] & [imm32] & [imm32] \\
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05 \aAArgH\shortWidthH & mov short [imm32], [imm32] & [imm32] & [imm32] \\
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05 \aAArgH\intWidthH & mov (int) [imm32], [imm32] & [imm32] & [imm32] \\
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\hline
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\end{tabularx}
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\paragraph{Description} Copies the source (operand one) value to the destination (operand two).
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\paragraph{Flags Affected} None.
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\subsection{AND}
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\OpcodeTable{01 /r /r}{and /r, /r}{Register}{Register}{Bit-wise ANDs \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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06 \rRArgH\byteWidthH & and byte /r, /r & /r & /r \\
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06 \rRArgH\shortWidthH & and short /r, /r & /r & /r \\
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06 \rRArgH\intWidthH & and (int) /r, /r & /r & /r \\
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06 \immRArgH\byteWidthH & and byte /imm8, /r & /imm8 & /r \\
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06 \immRArgH\shortWidthH & and short /imm16, /r & /imm16 & /r \\
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06 \immRArgH\intWidthH & and (int) /imm32, /r & /imm32 & /r \\
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\hline
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\end{tabularx}
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\paragraph{Description} Bitwise AND's the source (operand one) with the destination (operand two) storing the result in the destination. If the result of the operation is zero then the Zero Flag (ZF) is set.
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\paragraph{Flags Affected} ZF.
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\subsection{OR}
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\OpcodeTable{01 /r /r}{or /r, /r}{Register}{Register}{Bit-wise ORs \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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07 \rRArgH\byteWidthH & or byte /r, /r & /r & /r \\
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07 \rRArgH\shortWidthH & or short /r, /r & /r & /r \\
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07 \rRArgH\intWidthH & or (int) /r, /r & /r & /r \\
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07 \immRArgH\byteWidthH & or byte /imm8, /r & /imm8 & /r \\
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07 \immRArgH\shortWidthH & or short /imm16, /r & /imm16 & /r \\
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07 \immRArgH\intWidthH & or (int) /imm32, /r & /imm32 & /r \\
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\hline
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\end{tabularx}
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\paragraph{Description} Bitwise OR's the source (operand one) with the destination (operand two) storing the result in the destination. If the result of the operation is zero then the Zero Flag (ZF) is set.
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\paragraph{Flags Affected} ZF.
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\subsection{XOR}
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\OpcodeTable{01 /r /r}{xor /r, /r}{Register}{Register}{Bit-wise exclusive ORs \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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08 \rRArgH\byteWidthH & xor byte /r, /r & /r & /r \\
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08 \rRArgH\shortWidthH & xor short /r, /r & /r & /r \\
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08 \rRArgH\intWidthH & xor (int) /r, /r & /r & /r \\
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08 \immRArgH\byteWidthH & xor byte /imm8, /r & /imm8 & /r \\
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08 \immRArgH\shortWidthH & xor short /imm16, /r & /imm16 & /r \\
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08 \immRArgH\intWidthH & xor (int) /imm32, /r & /imm32 & /r \\
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\hline
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\end{tabularx}
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\paragraph{Description} Bitwise exclusive OR's (XOR) the source (operand one) with the destination (operand two) storing the result in the destination. If the result of the operation is zero then the Zero Flag (ZF) is set.
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\paragraph{Flags Affected} ZF.
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\subsection{NOT}
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\OpcodeTable{01 /r}{not /r}{Register}{None}{Bit-wise negates \textit{Operand 1} placing the result into \textit{Operand 1}.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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09 & xor /r & /r & None \\
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\hline
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\end{tabularx}
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\paragraph{Description} Bit-wise NOT's the source (operand one) in place.
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\paragraph{Flags Affected} None.
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\subsection{SHL}
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\OpcodeTable{01 /r /i8}{shl /r, /i8}{Register}{Immediate}{Shifts the bits of \textit{Operand 1} left \textit{Operand 2} times.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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0A \immRArgH\byteWidthH & shl byte imm8, /r & imm8 & /r \\
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0A \immRArgH\shortWidthH & shl short imm16, /r & imm16 & /r \\
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0A \immRArgH\intWidthH & shl (int) imm32, /r & imm32 & /r \\
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\hline
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\end{tabularx}
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\paragraph{Description} Shifts the destination (operand two) left \textit{operand one} times in place. If the source is smaller than before the operation the overflow flag (OF) is set. If the result of the operation is zero than the zero flag (ZF) is set.
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\paragraph{Flags Affected} OF and ZF.
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\subsection{SHR}
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\OpcodeTable{01 /r /i8}{shr /r, /i8}{Register}{Immediate}{Shifts the bits of \textit{Operand 1} right \textit{Operand 2} times.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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0B \immRArgH\byteWidthH & shr byte imm8, /r & imm8 & /r \\
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0B \immRArgH\shortWidthH & shr short imm16, /r & imm16 & /r \\
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0B \immRArgH\intWidthH & shr (int) imm32, /r & imm32 & /r \\
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\hline
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\end{tabularx}
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\paragraph{Description} Shifts the destination (operand two) right \textit{operand one} times in place. If the source is larger than before the operation the underflow flag (UF) is set. If the result of the operation is zero than the zero flag (ZF) is set.
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\paragraph{Flags Affected} UF and ZF.
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\subsection{NOP}
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\OpcodeTable{01}{nop}{None}{None}{No operation, increments the Program Counter by one.}
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%Oh this control flow will be interesting, juggling flags is not something I'm used to.
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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0C & nop & None & None \\
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\hline
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\end{tabularx}
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\paragraph{Description} Performs no operation except for incrementing the program counter by one.
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\paragraph{Flags Affected} None.
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\subsection{CMP}
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\OpcodeTable{01 /mod /r /r}{cmp /r, /r}{Register}{Register}{Subtracts \textit{Operand 2} from \textit{Operand 1} setting the Zero Flag if the result is zero. If \textit{Operand 2} is larger then the Sign Flag is set, otherwise the Sign Flag will be cleared.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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0D \rRArgH\intWidthH & cmp /r, /r & /r & /r \\
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\hline
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\end{tabularx}
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\paragraph{Description} Compares \textit{operand one} to \textit{operand two} by subtracting \textit{operand one} from \textit{operand two}, updating the status register with the results. If \textit{operand one} is larger than the result, and the result is not zero, the overflow flag (OF) is set. If \textit{operand one} is smaller than the result, and the result is not zero, the underflow flag (UF) is set. And if the result of the subtraction is zero the zero flag (ZF) is set.
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\paragraph{Flags Affected} OF, UF and ZF.
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\subsection{JMP}
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\OpcodeTable{01 /mod /i32}{jmp /i32}{Immediate}{None}{Unconditionally jumps to address \textit{Operand 1}.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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0E & jmp /imm32 & /imm32 & None \\
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\hline
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\end{tabularx}
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\paragraph{Description} Jumps unconditionally to the absolute memory address specified in \textit{operand one}.
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\paragraph{Flags Affected} None.
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\subsection{JZ}
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\OpcodeTable{01 /i32}{jz /i32}{Immediate}{None}{Jumps to address \textit{Operand 1} if the Zero Flag is set.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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0F & jz /imm32 & /imm32 & None \\
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\hline
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\end{tabularx}
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\paragraph{Description} Jumps to the absolute memory address specified in \textit{operand one} if the zero flag (ZF) is zet.
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\paragraph{Flags Affected} None.
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\subsection{JG}
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\OpcodeTable{01 /mod /i32}{jg /i32}{Immediate}{None}{Jumps to address \textit{Operand 1} if the Sign Flag is set.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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10 & jg /imm32 & /imm32 & None \\
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\hline
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\end{tabularx}
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\paragraph{Description} Jumps to the absolute memory address specified in \textit{operand one} if the overflow flag (OF) is zet.
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\paragraph{Flags Affected} None.
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\subsection{JL}
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\OpcodeTable{01 /mod /i32}{jl /i32}{Immediate}{None}{Jumps to address \textit{Operand 1} if the Sign Flag is not set.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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11 & jl /imm32 & /imm32 & None \\
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\hline
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\end{tabularx}
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\paragraph{Description} Jumps to the absolute memory address specified in \textit{operand one} if the underflow flag (UF) is zet.
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\paragraph{Flags Affected} None.
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%Maybe these in/out instructions could have a mode setting for choosing the width of the data written to the port.
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\subsection{Outb}
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\OpcodeTable{01 /r /r}{add /r, /r}{8-Bit}{Register}{Writes an 8-bit value from \textit{Operand 2} into port number \textit{Operand 1}.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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12 & outb /imm8, /imm8 & /imm8 & /imm8 \\
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\hline
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\end{tabularx}
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\paragraph{Description} Writes a byte of data to the port number specified in the destination (operand two).
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\paragraph{Flags Affected} None.
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\subsection{Inb}
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\OpcodeTable{01 /r /r}{inb /r, /r}{Register}{8-Bit}{Reads an 8-bit byte from the port number \textit{Operand 2}, writing it into \textit{Operand 1}.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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13 & inb /imm8, /r & /imm8 & /r \\
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\hline
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\end{tabularx}
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\paragraph{Description} Reads a byte of data from the port number in source (operand one) to the destination (operand two) register.
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\paragraph{Flags Affected} None.
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\subsection{HLT}
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\OpcodeTable{01}{hlt}{None}{None}{Halts the processor until a new interrupt is received.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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14 & hlt & None & None \\
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\hline
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\end{tabularx}
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\paragraph{Description} Halts the processor preventing it from executing the next instruction until an interrupt is received.
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\paragraph{Flags Affected} None.
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\subsection{CLI}\label{sec:cli}
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\OpcodeTable{01}{cli}{None}{None}{Clears the interrupt flag preventing the processor from receiving interrupts.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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15 & cli & None & None \\
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\hline
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\end{tabularx}
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\paragraph{Description} Clears interrupts, preventing the processor from responding to interrupts.
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\paragraph{Flags Affected} None.
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\subsection{ENI}\label{sec:eni}
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\OpcodeTable{01}{eni}{None}{None}{Sets the interrupt flag allowing the processor to receive interrupts.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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16 & eni & None & None \\
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\hline
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\end{tabularx}
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\paragraph{Description} Enables interrupts, allowing the processor to respond to interrupts.
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\paragraph{Flags Affected} None.
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\subsection{INT}\label{sec:int}
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\OpcodeTable{01 /i8}{int /i8}{Immediate}{None}{Triggers software interrupt number \textit{Operand 1}.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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17 & int /imm8 & /imm8 & None \\
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\hline
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\end{tabularx}
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\paragraph{Description} Triggers a software interrupt of type \textit{operand one} causing the flow of execution to jump to the registered subroutine in the Interrupt Vector Table at index \textit{operand one}.
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\paragraph{Flags Affected} None.
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\subsection{LIVT}\label{sec:livt}
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\OpcodeTable{00 /mod /i32}{livt /i32}{Immediate}{None}{Installs the Interrupt Vector Table located at memory address \textit{Operand 1}.}
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\begin{tabularx}{\textwidth}{ | c | X | c | c | }
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\hline
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Opcode & Instruction & Operand One & Operand Two \\
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\hline
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18 & livt /imm32 & /imm32 & None \\
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\hline
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\end{tabularx}
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\paragraph{Description} Registers a 1024 byte block of memory starting at \textit{operand one} as the Interrupt Vector Table.
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\paragraph{Flags Affected} None.
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