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Started to flesh out the opcodes but am having issues with Tex packaging trying to get the xint package for hopefully converting bit patterns to a hex code.

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Garritt McCune
2024-08-21 15:38:42 -05:00
parent c8ff04050e
commit c72b77ca19
2 changed files with 23 additions and 10 deletions
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chapter 2.tex
+18 -7
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@@ -52,7 +52,7 @@ Instructions are variable width with their total length being determined by the
\paragraph{Note} Figure \ref{fig:ModeSettingEncodingFigure} shows the options for the \textit{Mode} byte.
\end{figure}
\def\register{0000}\def\registerA{1000}
\def\registerBit{0000}\def\registerBitA{1000}
\def\eightBit{0001}\def\eightBitA{1001}
\def\sixteenBit{0010}\def\sixteenBitA{1010}
\def\thirtyBit{0100}\def\thirtyBitA{1100}
@@ -63,11 +63,11 @@ Instructions are variable width with their total length being determined by the
\hline
Operand & Immediate Value & Value As Address \\
\hline
Register & \register & 1000 \\
8-Bit & 0001 & 1001 \\
16-Bit & 0010 & 1010 \\
32-Bit & 0100 & 1100 \\
None & 1111 & 1111 \\
Register & \registerBit & \registerBitA \\
8-Bit & \eightBit & \eightBitA \\
16-Bit & \sixteenBit & \sixteenBitA \\
32-Bit & \thirtyBit & \thirtyBitA \\
None & \none & \none \\
\hline
\end{tabularx}
\caption{Operand Modes Bit Pattern}
@@ -77,7 +77,18 @@ Instructions are variable width with their total length being determined by the
\section{Instructions}
The /r represents a byte that specifies a register. /iX is for the immediate data type, where \textit{X} defines the width, which are 8, 16, or 32 bits.
\subsection{Add}
\OpcodeTable{01 /m /r /r}{add /r, /r}{Register}{Register}{Sums Operand 1 and Operand 2 placing the result into Operand 2.}
\begin{tabularx}{\textwidth}{ | X | X | X | X | }
\hline
Opcode & Instruction & Operand 1 & Operand 2 \\
\hline
01 \registerBit~\registerBit & add /r /r & Register & Register \\
01 \eightBit~\registerBit & add /i8 /r & Immediate & Register \\
01 \sixteenBit~\registerBit & add /i16 /r & Immediate & Register \\
01 \thirtyBit~\registerBit & add /i32 /r & Immediate & Register \\
\hline
\end{tabularx}
\paragraph{Description} Sums Operand 1 and Operand 2 placing the result into Operand 2 which must be a register.
\paragraph{Flags Affected} OF etc.
\subsection{Sub}
\OpcodeTable{01 /r /r}{sub /r, /r}{Register}{Register}{Subtracts \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
\subsection{Mul}
chapter 3.tex
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@@ -1,10 +1,12 @@
\chapter{Interrupts}
Interrupts are signals sent to the processor via the I/O pin, software interrupt (via the \hyperref[sec:int]{int} instruction) or by the processor detecting a fault (divide by zero for instance). When an interrupt occurs the processor will index the Interrupt Vector Table whose location is provided by the \hyperref[sec:livt]{livt} instruction.
\paragraph{Unknown Opcode} Interrupt 0. Pushes status flags and clears interrupts.
\paragraph{Unknown Opcode} Interrupt 0. Pushes status flags and clears interrupts. Called when an attempt is made executing a byte that is not a recognized opcode.
\paragraph{Divide by Zero} Interrupt 1. Pushes status flags and clears interrupts.
\paragraph{Divide by Zero} Interrupt 1. Pushes status flags and clears interrupts. Called when an attempt to divide any number by zero is made.
\paragraph{INT 2-31} Reserved for future use.
\paragraph{Break-point} Interrupt 2. Pushes status flags and clears the Stepping Flag. Called just before an opcode that has bit 7 set is to be executed.
\paragraph{INT 3-31} Reserved for future use.
\paragraph{INT 32-255} Open to be used by software services.