 glm94
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b31c1fbe76
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Started on a new figure to explain a new instruction layout, no more fixed length encoding, basically.
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2024-08-01 23:22:35 -05:00 |
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 Garritt McCune
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5cd831aeb9
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Added some more instructions to help flesh out the ISA section.
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2024-07-31 15:33:25 -05:00 |
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Garritt McCune
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04a06fc2ff
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Tweaked the figures a bit more.
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2024-07-24 16:27:52 -05:00 |
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Garritt McCune
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4acb5a7625
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Updated the register and memory layout figure.
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2024-07-23 14:52:56 -05:00 |
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Garritt McCune
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1b9910e908
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Started to mess around with setting up the figure for the layout of the registers and main memory.
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2024-07-22 16:09:00 -05:00 |
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Garritt McCune
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b1e3e585f4
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Minor tweaks and added a note or two.
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2024-07-19 16:26:21 -05:00 |
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Garritt McCune
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8003d389e9
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Updated the encoding layout figures.
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2024-07-19 15:54:34 -05:00 |
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Garritt McCune
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df15bb60e7
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Updated the Encoding Scheme section adding a 'operand mode' setting to the encoding as well changing the placement of the figures in that section.
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2024-07-19 13:50:44 -05:00 |
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glm94
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5c646a4835
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First opcode table setup.
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2024-07-19 00:53:29 -05:00 |
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glm94
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b6b340fd62
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Updated the figure for instruction encoding, mostly just example code for more proper figures.
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2024-07-18 00:24:44 -05:00 |
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glm94
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51c79d74aa
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Added the start of a second chapter for the ISA itself.
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2024-07-15 23:57:27 -05:00 |
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glm94
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70849bb698
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Added a little more about the registers and tweaked the code for the register bit layout figure.
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2024-06-16 01:38:41 -05:00 |
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glm94
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dcdf266cdd
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Initial commit and setup.
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2024-05-09 20:31:43 -05:00 |
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