 glm94
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3680d24d68
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Removed invalid Option nibble codes and refactored most of the instructions' section code to use the new command.
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2025-02-24 02:01:41 -06:00 |
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glm94
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02b3c9185d
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Updated the way I build the opcode table to be a little less repetitive. Now instead of making it an environment it is now a command that will build the arguments based on the 'Options' bit hexcode.
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2025-02-24 01:14:30 -06:00 |
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glm94
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43b8dd0119
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Added a conventions and data types section.
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2025-02-05 00:42:15 -06:00 |
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glm94
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472b9f839f
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Added a bit about the flags register
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2025-02-03 23:48:30 -06:00 |
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glm94
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d3ccd6678c
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Added some information about the memory layout and a figure for the bit ordering in the registers.
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2025-02-03 23:12:00 -06:00 |
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glm94
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f85a74bd83
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Updated chapter 1 to be more fleshed out.
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2025-02-02 00:15:44 -06:00 |
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glm94
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05adb3d0c9
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Added a few more instructions.
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2024-09-10 23:29:43 -05:00 |
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glm94
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892e34af93
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Fleshed out and updated all the current instructions' opcodes, arguments and functions.
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2024-09-03 23:21:14 -05:00 |
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glm94
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abbe9828e9
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Updated the way the encoding for the 'mode' byte works.
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2024-09-01 14:51:25 -05:00 |
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glm94
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e2e78a88fd
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Started the section on the supported interrupts just to get a few thoughts down.
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2024-08-19 19:21:49 -05:00 |
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glm94
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b31c1fbe76
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Started on a new figure to explain a new instruction layout, no more fixed length encoding, basically.
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2024-08-01 23:22:35 -05:00 |
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glm94
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5c646a4835
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First opcode table setup.
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2024-07-19 00:53:29 -05:00 |
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glm94
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b6b340fd62
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Updated the figure for instruction encoding, mostly just example code for more proper figures.
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2024-07-18 00:24:44 -05:00 |
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glm94
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51c79d74aa
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Added the start of a second chapter for the ISA itself.
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2024-07-15 23:57:27 -05:00 |
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glm94
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70849bb698
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Added a little more about the registers and tweaked the code for the register bit layout figure.
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2024-06-16 01:38:41 -05:00 |
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glm94
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dcdf266cdd
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Initial commit and setup.
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2024-05-09 20:31:43 -05:00 |
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