142 lines
8.0 KiB
TeX
142 lines
8.0 KiB
TeX
\chapter{Instruction Set Architecture}
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Instructions are variable width with their total length being determined by the mode setting byte that immediately follows the opcode byte. A break down of what a nibble means in the mode setting byte can be found in Figure \ref{fig:ModeSettingEncodingFigure}. Figure \ref{fig:opencoding} shows the layout of an instruction with the mode setting byte split down the middle to indicate the top nibble defines what \textit{Operand One} is meant to be interpreted as, followed by the lower nibble for \textit{Operand Two}. Depending on what mode is set for each operand there may be no bytes to follow the instruction (like in the case of nop) or there may be 8 bytes to follow (like in the case of mov [address], [address], assuming absolute addresses).
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\newcommand{\OpcodeTable}[5] {
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\noindent
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\begin{minipage}{\textwidth}
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\begin{tabularx}{\textwidth}{ | X | X | X | X | }
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\hline
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Opcode Hex & Instruction & Operand 1 & Operand 2 \\
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\hline
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#1 & #2 & #3 & #4 \\
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\hline
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\end{tabularx}
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\paragraph{Description} #5
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\end{minipage}
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}
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\def\gap{0.25pt}
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\def\minX{0}\def\maxX{\textwidth}
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\def\minY{-0.25}\def\maxY{0.25}
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\def\lnWidth{\textwidth / 4}
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\section{Instruction Layout}
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% Placement info here: https://en.wikibooks.org/wiki/LaTeX/Floats,_Figures_and_Captions#Figures
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% Paths: https://tikz.dev/tikz-paths
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\begin{figure}[ht]
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\begin{tikzpicture}
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%Opcode Byte
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\draw (\minX, 0) -- (\lnWidth, 0) node[midway, below=1em] {Opcode};
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\draw (\minX, \minY) node[below] {7} -- (\minX, \maxY);
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\draw (\lnWidth, \minY) -- (\lnWidth, \maxY) node[above] {7};
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%Mode setting byte
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\draw (\lnWidth, 0) -- (\lnWidth * 2, 0) node[midway, above=1em] (ModeSettingByteLabel) {Mode};
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\draw node[above of=ModeSettingByteLabel] {(if required)};
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\draw (\lnWidth, \minY) node[below] {0} -- (\lnWidth, \maxY);
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\draw (\lnWidth * 2, \minY) node[below] {0} -- (\lnWidth * 2, \maxY);
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\draw (\lnWidth + \lnWidth / 2, \minY) node[below] (ModeByteMiddleLabel) {4 3} -- (\lnWidth + \lnWidth / 2, \maxY);
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%Operand One
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\draw (\lnWidth * 2, 0) -- (\lnWidth * 3, 0) node[midway, below=1em] (OperOneLabel) {Operand One};
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\draw (\lnWidth * 2, \minY) -- (\lnWidth * 2, \maxY) node[above] {31/15/7};
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\draw (\lnWidth * 3, \minY) node[below] {0} -- (\lnWidth * 3, \maxY);
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\draw node[below of=OperOneLabel] {(if required)};
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%Operand Two
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\draw (\lnWidth * 3, 0) -- (\lnWidth * 4, 0) node[midway, below=1em] (OperTwoLabel) {Operand Two};
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\draw (\lnWidth * 3, \minY) -- (\lnWidth * 3, \maxY) node[above] {31/15/7} node[above=1.5em] {Operand Widths Based on Mode};
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\draw (\textwidth, \minY) node[below] {0} -- (\textwidth, \maxY);
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\draw node[below of=OperTwoLabel] {(if required)};
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\end{tikzpicture}
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\caption{Encoding}
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\label{fig:opencoding} % https://www.overleaf.com/learn/latex/Referencing_Figures
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\paragraph{Note} Figure \ref{fig:ModeSettingEncodingFigure} shows the options for the \textit{Mode} byte.
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\end{figure}
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\def\registerBit{0000}\def\registerBitA{1000}
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\def\eightBit{0001}\def\eightBitA{1001}
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\def\sixteenBit{0010}\def\sixteenBitA{1010}
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\def\thirtyBit{0100}\def\thirtyBitA{1100}
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\def\none{1111}
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\begin{figure}
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\begin{tabularx}{\textwidth}{ | X | X | X | }
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\hline
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Operand & Immediate Value & Value As Address \\
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\hline
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Register & \registerBit & \registerBitA \\
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8-Bit & \eightBit & \eightBitA \\
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16-Bit & \sixteenBit & \sixteenBitA \\
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32-Bit & \thirtyBit & \thirtyBitA \\
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None & \none & \none \\
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\hline
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\end{tabularx}
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\caption{Operand Modes Bit Pattern}
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\label{fig:ModeSettingEncodingFigure} % https://www.overleaf.com/learn/latex/Referencing_Figures
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\end{figure}
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\clearpage
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\section{Instructions}
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The /r represents a byte that specifies a register. /iX is for the immediate data type, where \textit{X} defines the width, which are 8, 16, or 32 bits.
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\subsection{Add}
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\begin{tabularx}{\textwidth}{ | X | X | X | X | }
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\hline
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Opcode & Instruction & Operand 1 & Operand 2 \\
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\hline
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01 \registerBit~\registerBit & add /r /r & Register & Register \\
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01 \eightBit~\registerBit & add /i8 /r & Immediate & Register \\
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01 \sixteenBit~\registerBit & add /i16 /r & Immediate & Register \\
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01 \thirtyBit~\registerBit & add /i32 /r & Immediate & Register \\
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\hline
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\end{tabularx}
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\paragraph{Description} Sums Operand 1 and Operand 2 placing the result into Operand 2 which must be a register.
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\paragraph{Flags Affected} OF etc.
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\subsection{Sub}
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\OpcodeTable{01 /r /r}{sub /r, /r}{Register}{Register}{Subtracts \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
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\subsection{Mul}
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\OpcodeTable{01 /r /r}{mul /r, /r}{Register}{Register}{Multiplies \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
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\subsection{Div}
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\OpcodeTable{01 /r /r}{div /r, /r}{Register}{Register}{Divides \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
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\subsection{Mov}
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\OpcodeTable{04 /mod /r /r}{mov /mod /r, /r}{Register}{Register}{Copies the 32-bit value from \textit{Operand 2} to \textit{Operand 1}.}
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\subsection{AND}
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\OpcodeTable{01 /r /r}{and /r, /r}{Register}{Register}{Bit-wise ANDs \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
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\subsection{OR}
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\OpcodeTable{01 /r /r}{or /r, /r}{Register}{Register}{Bit-wise ORs \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
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\subsection{XOR}
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\OpcodeTable{01 /r /r}{xor /r, /r}{Register}{Register}{Bit-wise exclusive ORs \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
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\subsection{NOT}
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\OpcodeTable{01 /r}{not /r}{Register}{None}{Bit-wise negates \textit{Operand 1} placing the result into \textit{Operand 1}.}
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\subsection{SHL}
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\OpcodeTable{01 /r /i8}{shl /r, /i8}{Register}{Immediate}{Shifts the bits of \textit{Operand 1} left \textit{Operand 2} times.}
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\subsection{SHR}
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\OpcodeTable{01 /r /i8}{shr /r, /i8}{Register}{Immediate}{Shifts the bits of \textit{Operand 1} right \textit{Operand 2} times.}
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\subsection{NOP}
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\OpcodeTable{01}{nop}{None}{None}{No operation, increments the Program Counter by one.}
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%Oh this control flow will be interesting, juggling flags is not something I'm used to.
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\subsection{CMP}
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\OpcodeTable{01 /mod /r /r}{cmp /r, /r}{Register}{Register}{Subtracts \textit{Operand 2} from \textit{Operand 1} setting the Zero Flag if the result is zero. If \textit{Operand 2} is larger then the Sign Flag is set, otherwise the Sign Flag will be cleared.}
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\subsection{JMP}
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\OpcodeTable{01 /mod /i32}{jmp /i32}{Immediate}{None}{Unconditionally jumps to address \textit{Operand 1}.}
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\subsection{JZ}
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\OpcodeTable{01 /i32}{jz /i32}{Immediate}{None}{Jumps to address \textit{Operand 1} if the Zero Flag is set.}
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\subsection{JG}
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\OpcodeTable{01 /mod /i32}{jg /i32}{Immediate}{None}{Jumps to address \textit{Operand 1} if the Sign Flag is set.}
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\subsection{JL}
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\OpcodeTable{01 /mod /i32}{jl /i32}{Immediate}{None}{Jumps to address \textit{Operand 1} if the Sign Flag is not set.}
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%Maybe these in/out instructions could have a mode setting for choosing the width of the data written to the port.
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\subsection{Outb}
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\OpcodeTable{01 /r /r}{add /r, /r}{8-Bit}{Register}{Writes an 8-bit value from \textit{Operand 2} into port number \textit{Operand 1}.}
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\subsection{Inb}
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\OpcodeTable{01 /r /r}{inb /r, /r}{Register}{8-Bit}{Reads an 8-bit byte from the port number \textit{Operand 2}, writing it into \textit{Operand 1}.}
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\subsection{HLT}
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\OpcodeTable{01}{hlt}{None}{None}{Halts the processor until a new interrupt is received.}
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\subsection{CLI}\label{sec:cli}
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\OpcodeTable{01}{cli}{None}{None}{Clears the interrupt flag preventing the processor from receiving interrupts.}
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\subsection{ENI}\label{sec:eni}
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\OpcodeTable{01}{eni}{None}{None}{Sets the interrupt flag allowing the processor to receive interrupts.}
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\subsection{INT}\label{sec:int}
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\OpcodeTable{01 /i8}{int /i8}{Immediate}{None}{Triggers software interrupt number \textit{Operand 1}.}
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\subsection{LIVT}\label{sec:livt}
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\OpcodeTable{00 /mod /i32}{livt /i32}{Immediate}{None}{Installs the Interrupt Vector Table located at memory address \textit{Operand 1}.} |