 Garritt McCune
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eba9778993
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Created a basic setup for the figure for the memory layout / map.
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2025-02-04 15:17:13 -06:00 |
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 glm94
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f85a74bd83
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Updated chapter 1 to be more fleshed out.
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2025-02-02 00:15:44 -06:00 |
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Garritt McCune
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efb8bf8883
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Further refined some details about how ADD will work which will impact the way the rest of the processor will behave.
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2024-08-22 14:23:04 -05:00 |
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Garritt McCune
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c8ff04050e
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Updated the look of references
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2024-08-20 16:34:35 -05:00 |
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glm94
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e2e78a88fd
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Started the section on the supported interrupts just to get a few thoughts down.
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2024-08-19 19:21:49 -05:00 |
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Garritt McCune
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1b9910e908
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Started to mess around with setting up the figure for the layout of the registers and main memory.
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2024-07-22 16:09:00 -05:00 |
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glm94
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5c646a4835
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First opcode table setup.
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2024-07-19 00:53:29 -05:00 |
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glm94
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51c79d74aa
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Added the start of a second chapter for the ISA itself.
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2024-07-15 23:57:27 -05:00 |
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glm94
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70849bb698
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Added a little more about the registers and tweaked the code for the register bit layout figure.
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2024-06-16 01:38:41 -05:00 |
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glm94
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dcdf266cdd
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Initial commit and setup.
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2024-05-09 20:31:43 -05:00 |
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