src/cmd/t8.s (TMG): add opcode comments extraced from sys/sop.s

This commit is contained in:
phil
2021-08-24 15:37:00 -04:00
parent 580d181f6e
commit 86f6b7f3d6
+43 -43
View File
@@ -4,50 +4,50 @@
" no iot ops are defined
" system cal entries are defined
"
dac = 0040000
jms = 0100000
dzm = 0140000
lac = 0200000
xor = 0240000
add = 0300000
tad = 0340000
xct = 0400000
isz = 0440000
and = 0500000
sad = 0540000
jmp = 0600000
eae = 0640000
i = 020000
opr = 0740000
law = opr i
cma = opr 1
cml = opr 2
ral = opr 010
rar = opr 020
sma = opr 0100
sza = opr 0200
snl = opr 0400
skp = opr 01000
spa = opr 01100
sna = opr 01200
szl = opr 01400
cll = opr 04000
cla = opr 010000
las = opr 010004
lrs = eae 0500
lrss = i lrs
lls = eae 0600
llss = i lls
als = eae 0700
alss = i als
lacq = eae 01002
lacs = eae 01001
clq = eae 010000
omq = eae 2
cmq = eae 4
lmq = eae 012000
dac = 0040000 " MEM: deposit AC
jms = 0100000 " MEM: jump to subroutine
dzm = 0140000 " MEM: deposit zero to memory
lac = 0200000 " MEM: load AC
xor = 0240000 " MEM: XOR with AC
add = 0300000 " MEM: one's complement add
tad = 0340000 " MEM: two's complement add
xct = 0400000 " MEM: execute
isz = 0440000 " MEM: increment and skip if zero
and = 0500000 " MEM: AND
sad = 0540000 " MEM: skip if AC different
jmp = 0600000 " MEM: jump
eae = 0640000 " Extended Arithmetic Element
i = 020000 " indirect
opr = 0740000 " Operator (bit encoded)
law = opr i " OPR: load accumulator with (instr)
cma = opr 1 " OPR: complement AC
cml = opr 2 " OPR: complement LINK
ral = opr 010 " OPR: rotate AC left
rar = opr 020 " OPR: rotate AC right
sma = opr 0100 " OPR: skip on minus AC
sza = opr 0200 " OPR: skip on zero AC
snl = opr 0400 " OPR: skip on non-zero link
skp = opr 01000 " OPR: skip unconditionally
spa = opr 01100 " OPR: skip on positive AC
sna = opr 01200 " OPR: skip on non-zero AC
szl = opr 01400 " OPR: skip on zero link
cll = opr 04000 " OPR: clear link
cla = opr 010000 " OPR: clear AC
las = opr 010004 " OPR: load AC from switches
lrs = eae 0500 " EAE: long right shift
lrss = i lrs " EAE: long right shift, signed
lls = eae 0600 " EAE: long left shift
llss = i lls " EAE: long left shift, signed
als = eae 0700 " EAE: AC left shift
alss = i als " EAE: AC left shift, signed
lacq = eae 01002 " EAE: load AC with MQ
lacs = eae 01001 " EAE: load AC with SC (not used)
clq = eae 010000 " EAE: clear MQ
omq = eae 2 " EAE: OR MQ into AC
cmq = eae 4 " EAE: complement MQ
lmq = eae 012000 " EAE: load MQ from AC
sys = i
sys = i " CAL instruction w/ indirect bit
save = 1
open = 3
read = 4