54 lines
4.3 KiB
TeX
54 lines
4.3 KiB
TeX
\chapter{Introduction}
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This is an attempt to distill what I know about how computers work into some kind of emulator / simulator. I'm curious to see if what I know at the moment is enough to allow me to emulate a general purpose computer. It turns out that it take quite a different skillset compared to writing web applications or desktop applications. But I realize that, while I understand the concepts that underpin what I do day to day, I don't have an intuitive understanding of the hardware. This has become painfully evident pretty much immediately after I started this project. An ISA should be simple, add, subtract, copy, etc., but the you have to consider the state the processor will be in after each instruction.
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\section{Registers}
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Thirty-two general purpose registers are available for program code to use however it wishes. The base name for the general purpose registers is \quotes{r} follows by an unpadded number, such as \quotes{r28}. These numbers do not follow a zero-based index scheme, \quotes{r29} is the twenty-ninth register. Using the base name implies full width, a \quotes{word}, when reading or writing from or to the register respectively.
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In addition to the general purpose registers there is also a base pointer (bp), stack pointer (sp) and an instruction pointer (ip). The base pointer and the stack pointer may be set directly using the \hyperref[sec:mov]{mov} instruction, which allows the programmer to set up a stack frame. The instruction pointer can only be set with a branching operation like \hyperref[sec:jmp]{jmp} or a call to a subroutine with the \hyperref[sec:call]{call} instruction. One final register that can only be indirectly set is the \quotes{flags} register. This register, like the others, is one word wide meaning it can store thirty-two flags. Currently only three flags are present, the Zero, Underflow and Overflow flags. These flags are only affected by arthmetic operations and generally read by branching instructions like \hyperref[sec:jmp]{jmp}.
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\begin{figure}[h]
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\begin{tikzpicture}
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%\draw[help lines] (-8,-3) grid (8,3);
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\node [draw, fit={(-6, 0) (-1, -0.5)}, label=center:r1] (r1) {};
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\node [draw=none, fit={(-6, -1) (-1, -1.5)}, label=center:...] (ellipsis) {};
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\node [draw, fit={(-6, -2) (-1, -2.5)}, label=center:r32] (r32) {};
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\node [draw, fit={(-3.0, 1.5) (2.0, 1.0)}, label=center:Flags Register] (flags) {};
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\node [draw, fit={(0, 0) (5, -0.5)}, label=center:Instruction Pointer (ip)] (ip) {};
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\node [draw, fit={(0, -1.0) (5, -1.5)}, label=center:Base Pointer (ip)] (bp) {};
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\node [draw, fit={(0, -2.0) (5, -2.5)}, label=center:Stack Pointer (ip)] (sp) {};
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\draw (r1);
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\node at (r1.north) [above] {General Purpose};
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\node at (r1.north west) [above] {31};
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\node at (r1.north east) [above] {0};
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\draw (ellipsis);
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\draw (r32);
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\draw (flags);
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\node at (flags.north) [above] {Status Register};
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\node at (flags.north west) [above] {31};
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\node at (flags.north east) [above] {0};
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\draw (ip);
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\node at (ip.north) [above] {Program Status};
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\node at (ip.north west) [above] {31};
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\node at (ip.north east) [above] {0};
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\draw (bp);
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\draw (sp);
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\end{tikzpicture}
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\caption{Bit Ordering}
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\label{fig:registerbitlayout} % https://www.overleaf.com/learn/latex/Referencing_Figures
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\end{figure}
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\begin{description}
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\item In summary, the available registers are as follows:
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\item[General Purpose] Thirty-two general purpose registers that are the width of a \textit{word} and numbered \quotes{r1} through \quotes{r32}
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\item[Base Pointer (bp)] Points to the call location when a function call is made
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\item[Stack Pointer (sp)] points to the end of the last argument after a function call is executed, which may be the return address of the stack
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\item[Instruction Pointer (ip)] Points to the next instruction to execute and advanced by the width of an instruction. Set by jump or call instructions to the location specified by the instruction.
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\end{description}
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\section{Memory}
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The memory layout is quite simple, much like many modern machines it is a linear memory map. The address bus is thrity-two bits wide, the same width of the data bus, meaning at most there is 2\textsuperscript{32} of addressable memory. Like contemprary machines the top of memory starts at address 0x00000000 and grows downward toward 0xFFFFFFFF. |