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Added some more instructions to help flesh out the ISA section.

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Garritt McCune
2024-07-31 15:33:25 -05:00
parent 04a06fc2ff
commit 5cd831aeb9
1 changed files with 46 additions and 6 deletions
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chapter 2.tex
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@@ -53,11 +53,11 @@ All instructions are a fixed width of 32-bits. There are two basic encoding sche
\hline
Bit Pattern & Destination & Source \\
\hline
000 & Register & Register \\
001 & Register & 8 Bit Immediate \\
010 & Register & 32 Bit Immediate \\
011 & 8 Bit Immediate & Register \\
100 & 32 Bit Immediate & Register \\
0000 & Register & Register \\
0001 & Register & 8 Bit Immediate \\
0010 & Register & 32 Bit Immediate \\
0011 & 8 Bit Immediate & Register \\
0100 & 32 Bit Immediate & Register \\
\hline
\end{tabularx}
\caption{Addressing Mode}
@@ -70,5 +70,45 @@ All instructions are a fixed width of 32-bits. There are two basic encoding sche
The /r represents a byte that specifies a register. /iX is for the immediate data type, where \textit{X} defines the width, which are 8, 16, or 32 bits.
\subsection{Add}
\OpcodeTable{01 /r /r}{add /r, /r}{Register}{Register}{Sums \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
\subsection{Sub}
\OpcodeTable{01 /r /r}{sub /r, /r}{Register}{Register}{Subtracts \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
\subsection{Mul}
\OpcodeTable{01 /r /r}{mul /r, /r}{Register}{Register}{Multiplies \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
\subsection{Div}
\OpcodeTable{01 /r /r}{div /r, /r}{Register}{Register}{Divides \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
\subsection{Mov}
\OpcodeTable{04 /mod /r /r}{mov /mod /r, /r}{Register}{Register}{Copies the 32-bit value from \textit{Operand 2} to \textit{Operand 1}.}}
\OpcodeTable{04 /mod /r /r}{mov /mod /r, /r}{Register}{Register}{Copies the 32-bit value from \textit{Operand 2} to \textit{Operand 1}.}
\subsection{AND}
\OpcodeTable{01 /r /r}{and /r, /r}{Register}{Register}{Bit-wise ANDs \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
\subsection{OR}
\OpcodeTable{01 /r /r}{or /r, /r}{Register}{Register}{Bit-wise ORs \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
\subsection{XOR}
\OpcodeTable{01 /r /r}{xor /r, /r}{Register}{Register}{Bit-wise exclusive ORs \textit{Operand 1} and \textit{Operand 2} placing the result into \textit{Operand 1}.}
\subsection{NOT}
\OpcodeTable{01 /r}{not /r}{Register}{None}{Bit-wise negates \textit{Operand 1} placing the result into \textit{Operand 1}.}
\subsection{NOP}
\OpcodeTable{01}{nop}{None}{None}{No operation, increments the Program Counter by one.}
%Oh this control flow will be interesting, juggling flags is not something I'm used to.
\subsection{CMP}
\OpcodeTable{01 /mod /r /r}{cmp /r, /r}{Register}{Register}{Subtracts \textit{Operand 2} from \textit{Operand 1} setting the Zero Flag if the result is zero. If \textit{Operand 2} is larger then the Sign Flag is set, otherwise the Sign Flag will be cleared.}
\subsection{JMP}
\OpcodeTable{01 /mod /i32}{jmp /i32}{Immediate}{None}{Unconditionally jumps to address \textit{Operand 1}.}
\subsection{JZ}
\OpcodeTable{01 /i32}{jz /i32}{Immediate}{None}{Jumps to address \textit{Operand 1} if the Zero Flag is set.}
\subsection{JG}
\OpcodeTable{01 /mod /i32}{jg /i32}{Immediate}{None}{Jumps to address \textit{Operand 1} if the Sign Flag is set.}
\subsection{JL}
\OpcodeTable{01 /mod /i32}{jl /i32}{Immediate}{None}{Jumps to address \textit{Operand 1} if the Sign Flag is not set.}
%Maybe these in/out instructions could have a mode setting for choosing the width of the data written to the port.
\subsection{Outb}
\OpcodeTable{01 /r /r}{add /r, /r}{8-Bit}{Register}{Writes an 8-bit value from \textit{Operand 2} into port number \textit{Operand 1}.}
\subsection{Inb}
\OpcodeTable{01 /r /r}{inb /r, /r}{Register}{8-Bit}{Reads an 8-bit byte from the port number \textit{Operand 2}, writing it into \textit{Operand 1}.}
\subsection{HLT}
\OpcodeTable{01}{hlt}{None}{None}{Halts the processor until a new interrupt is received.}
\subsection{CLI}
\OpcodeTable{01}{cli}{None}{None}{Clears the interrupt flag preventing the processor from receiving interrupts.}
\subsection{ENI}
\OpcodeTable{01}{eni}{None}{None}{Sets the interrupt flag allowing the processor to receive interrupts.}