145 lines
6.6 KiB
TeX
145 lines
6.6 KiB
TeX
\documentclass[a4paper,12pt]{book}
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\usepackage{tikz}
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\usepackage{hyperref}
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\hypersetup{
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linktoc=all
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}
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\title{Unnamed Machine}
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\author{A Very Terrible 16-bit Machine}
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\newcommand{\OpcodeTable}[4] {
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\begin{tabular}{ c c c c }
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\hline
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Opcode & Mnemonic & Operand 1 & Operand 2 \\
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\hline\hline
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#1 & #2 & #3 & #4 \\
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\hline
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\end{tabular}
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}
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\begin{document}
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\maketitle
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\tableofcontents
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\chapter{Overview}
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\section{Introduction}
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This is a very poorly thought out 16-bit machine, but you've got to start somewhere. Currently debating between a CPU status register, 80x86 style, or just placing arithmetic results into a predetermined register. This is more of a load–store architecture to try and keep the instruction set simple. The machine will be big-endian.
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\section{Registers}
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The following are the general purpose registers that can be used.
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\begin{itemize}
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\item[] R1
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\item[] ...
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\item[] R8
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\end{itemize}
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Additionally, there will be a special status register that will be a signed 16 bit register that the compare and jump instructions will read or write to when determining what action, if any, they'll take.
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\section{Memory Model}
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Memory will be implicitly mapped I/O. The bottom 3201 bytes of memory will be reserved for the keyboard input and graphics.
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A single byte is reserved for the keyboard's input. The current key will be stored in byte 0xF37E, with the most significant bit being a flag indicating that the keyboard
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is ready to be read from. This means that the character encoding is actually 7 bits.
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Video memory starts at 0xF37F (62335 decimal), and every byte represents an ASCII character in monochrome.
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\begin{figure}[!htb]
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\centering
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\begin{tikzpicture}
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\fill[gray!5] (0,0)rectangle(5,10);
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%\draw (0,10) .. controls (-2,6) and (-2,4) .. (0,1);
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%\draw (0,10) arc (0:180:3cm);
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\draw (0,10) -- (5,10);
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\draw (0,1) -- node[above] {Video 0xF37F} (5,1);
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\draw (0,0) -- (5,0);
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\node[label=right:Top 0x0000] at (5,10) {};
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\node[label=right:Bottom 0xFFFF] at (5,0) {};
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\end{tikzpicture}
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\caption{Memory Layout}
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\end{figure}
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\chapter{Instruction Set Architecture}
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\section{Instruction Encoding}
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Instructions are fixed to exactly one byte (8 bits).
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Instructions that work with two operands the register for operand one will be encoded in the three least significant bits. So an instruction with format XXXX X000 will use Register 1 and so forth all the way to XXXX X111, which will be Register 8.
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%https://tex.stackexchange.com/questions/32598/force-latex-image-to-appear-in-the-section-in-which-its-declared
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\begin{figure}[!htb]
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\centering
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\begin{tabular}{ c c }
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\hline
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Instruction & Register \\
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\hline\hline
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0000 0 & 000 \\
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\hline
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\end{tabular}
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\caption{Encoding Layout}
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\end{figure}
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\section{Notes}
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For the opcodes that load or store data at the assembly language level we could have the mnemonics
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"store" and "load" and have the assembler pick the opcode based on the inclusion of the word "byte"
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or "word" for two bytes. That would make the assembly easier to read but put a bit more work on the
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assembler.
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\section{STOB (Store Byte)}
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\OpcodeTable{0x20}{stob}{Register}{Address}\\[6pt]
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Stores a single byte (the lower nibble) from a register to a memory address.
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\section{STOW (Store Machine Word)}
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\OpcodeTable{0x20}{stow}{Register}{Address}\\[6pt]
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Stores a machine word from a register to a memory address.
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\section{LA (Load Address)}
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\OpcodeTable{0x00}{la}{Register}{Address}\\[6pt]
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Loads an address (2 bytes) into the register.
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\section{LODB (Load Byte)}
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\OpcodeTable{0x20}{lodb}{Register}{Register}\\[6pt]
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Loads a single byte into a register from a memory address in the second operand register, zeroing out the high nibble.
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\section{LODW (Load Machine Word)}
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\OpcodeTable{0x20}{lodw}{Register}{Register}\\[6pt]
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Loads a word into a register from a memory address in the second operand register.
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\section{LODWI (Load Immediate Word)}
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\OpcodeTable{0x00}{lodwi}{Register}{Constant}\\[6pt]
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Loads an immediate machine word into the register clearing the high nibble if the value is less then 256.
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\section{CMP (Compare)}
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\OpcodeTable{0x20}{cmp}{Register}{Register}\\[6pt]
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Compares two registers and somewhere sets a result in the status register.
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\section{CMPI (Compare Immediate)}
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\OpcodeTable{0x00}{cmpi}{Register}{Constant}\\[6pt]
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Compares an immediate 2 byte value to the contents of a register setting the status register accordingly.
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\section{ADD (Add)}
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\OpcodeTable{0x20}{add}{Register}{Register}\\[6pt]
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Performs addition on a register with a value from another (or the same) register.
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\section{SUB (Subtract)}
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\OpcodeTable{0x20}{sub}{Register}{Register}\\[6pt]
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Performs subtraction on a register with a value from another (or the same) register.
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\section{JMP (Jump)}
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\OpcodeTable{0x20}{jmp}{Address}{None}\\[6pt]
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Jumps unconditionally to a memory address.
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\section{JZ (Jump if Zero)}
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\OpcodeTable{0x20}{jz}{Register}{None}\\[6pt]
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Jumps to a memory address if the status flag is zero.
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\section{JG (Jump if Greater Than)}
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\OpcodeTable{0x70}{jg}{Address}{None}\\[6pt]
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Jump to the Address if the status flag is greater than zero.
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\section{JL (Jump if Less Than)}
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\OpcodeTable{0x00}{jl}{Address}{None}\\[6pt]
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Jumps to the address if the status flag is less than zero.
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\section{AND (Logical AND)}
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\OpcodeTable{0x00}{and}{Register}{Register}\\[6pt]
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Logical ANDs the two registers together storing the result in operand 1.
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\section{XOR (Logical Exclusive OR)}
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\OpcodeTable{0x00}{xor}{Register}{Register}\\[6pt]
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Logical XORs the two registers together storing the result in operand 1.
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\section{OR (Logical OR)}
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\OpcodeTable{0x00}{or}{Register}{Register}\\[6pt]
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Logical ORs the two registers together storing the result in operand 1.
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\section{NOT (Logical Negation)}
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\OpcodeTable{0x00}{not}{Register}{None}\\[6pt]
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Inverts the bits of the target register.
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\section{SHR (Shift Right)}
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\OpcodeTable{0x00}{shr}{Register}{Constant}\\[6pt]
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Bit-wise shifts the contents of the register right Constant number of times.
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\section{SHL (Shift Left)}
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\OpcodeTable{0x00}{shl}{Register}{Constant}\\[6pt]
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Bit-wise shifts the contents of the register left Constant number of times.
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\section{INC (Increment)}
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\OpcodeTable{0x00}{inc}{Register}{None}\\[6pt]
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Increments the contents of the register by one. Over-flows will not be reported.
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\section{DEC (Decrement)}
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\OpcodeTable{0x00}{dec}{Register}{None}\\[6pt]
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Decrements the contents of the register by one. Under-flows will not be reported.
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\section{NOP (No Operation)}
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\OpcodeTable{0x00}{nop}{None}{None}\\[6pt]
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Skips a clock cycle, incrementing the program counter by one.
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\end{document}
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