Added a command to make generating an opcode table a one liner. Updated the ISA.
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+41
-75
@@ -1,15 +1,25 @@
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\documentclass{book}
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\documentclass[a4paper,12pt]{book}
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\usepackage{tikz}
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\title{Unnamed Machine}
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\author{A Very Terrible 16-bit Machine}
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\newcommand{\OpcodeTable}[4] {
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\begin{tabular}{ c c c c }
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\hline
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Opcode & Mnemonic & Operand 1 & Operand 2 \\
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\hline\hline
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#1 & #2 & #3 & #4 \\
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\hline
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\end{tabular}
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}
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\begin{document}
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\maketitle
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\tableofcontents
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\chapter{Overview}
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\section{Introduction}
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This is a very poorly thought out 16-bit machine, but you've got to start somewhere. Currently debating between a CPU status register, 80x86 style, or just placing arithmetic results into a predetermined register. This is more of a load–store architecture to try and keep the instruction set simple.
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This is a very poorly thought out 16-bit machine, but you've got to start somewhere. Currently debating between a CPU status register, 80x86 style, or just placing arithmetic results into a predetermined register. This is more of a load–store architecture to try and keep the instruction set simple. The machine will be big-endian.
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\section{Registers}
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The following are the general purpose registers that can be used.
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\begin{itemize}
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@@ -39,7 +49,7 @@
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\chapter{Instruction Set Architecture}
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\section{Instruction Encoding}
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Instructions are fixed to exactly one byte (8 bits).
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Instructions that work with two operands the register for operand one will be encoded in the three least significant bits. So an instruction with format XXXX X000 will use Register 1 and so forth all the way to the pattern XXXX X111, which will be Register 8.
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Instructions that work with two operands the register for operand one will be encoded in the three least significant bits. So an instruction with format XXXX X000 will use Register 1 and so forth all the way to XXXX X111, which will be Register 8.
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\begin{figure}
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\centering
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\begin{tabular}{ c c }
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@@ -52,87 +62,41 @@
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\caption{Encoding Layout}
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\end{figure}
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\section{STOB (Store Byte)}
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\begin{tabular}{ c c c c }
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\hline
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Opcode & Mnemonic & Operand 1 & Operand 2 \\
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\hline\hline
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0x20 & stob & Register & Memory Address \\
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\hline
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\end{tabular}\\[6pt]
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Stores a single byte (the lower nibble) from a register to a memory address.
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\OpcodeTable{0x20}{stob}{Register}{Address}\\[6pt]
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Stores a single byte (the lower nibble) from a register to a memory address.
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\section{STOW (Store Machine Word)}
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\begin{tabular}{ c c c c }
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\hline
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Opcode & Mnemonic & Operand 1 & Operand 2 \\
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\hline\hline
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0x20 & stow & Register & Memory Address \\
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\hline
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\end{tabular}\\[6pt]
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Stores a machine word from a register to a memory address.
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\OpcodeTable{0x20}{stow}{Register}{Address}\\[6pt]
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Stores a machine word from a register to a memory address.
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\section{LODB (Load Byte)}
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\begin{tabular}{ c c c c }
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\hline
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Opcode & Mnemonic & Operand 1 & Operand 2 \\
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\hline\hline
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0x20 & lodb & Register & Address \\
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\hline
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\end{tabular}\\[6pt]
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Loads a single byte into a register from a memory address.
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\OpcodeTable{0x20}{lodb}{Register}{Address}\\[6pt]
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Loads a single byte into a register from a memory address, zeroing out the high nibble.
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\section{LODW (Load Machine Word)}
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\begin{tabular}{ c c c c }
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\hline
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Opcode & Mnemonic & Operand 1 & Operand 2 \\
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\hline\hline
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0x20 & lodw & Register & Address \\
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\hline
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\end{tabular}\\[6pt]
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Loads a word into a register from a memory address.
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\OpcodeTable{0x20}{lodw}{Register}{Address}\\[6pt]
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Loads a word into a register from a memory address.
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\section{LABR (Load Byte from Address)}
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\OpcodeTable{0x20}{stow}{Register}{None}\\[6pt]
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Loads a single byte, zeroing out the high nibble, with the address found in the register.
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\section{LAWR (Load Word from Address)}
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\OpcodeTable{0x20}{lawr}{Register}{None}\\[6pt]
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Loads a machine word with the address found in the register.
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\section{CMP (Compare)}
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\begin{tabular}{ c c c c }
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\hline
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Opcode & Mnemonic & Operand 1 & Operand 2 \\
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\hline\hline
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0x80 & cmp & Register & Register \\
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\hline
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\end{tabular}\\[6pt]
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Compares two registers and somewhere sets a result, maybe in register 1?
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\OpcodeTable{0x20}{cmp}{Register}{Register}\\[6pt]
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Compares two registers and somewhere sets a result, maybe in register 1?
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\section{ADD (Add)}
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\begin{tabular}{ c c c c }
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\hline
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Opcode & Mnemonic & Operand 1 & Operand 2 \\
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\hline\hline
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0x40 & add & Register & Register \\
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\hline
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\end{tabular}\\[6pt]
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Performs addition on a register with a value from another (or the same) register.
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\OpcodeTable{0x20}{add}{Register}{Register}\\[6pt]
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Performs addition on a register with a value from another (or the same) register.
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\section{SUB (Subtract)}
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\begin{tabular}{ c c c c }
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\hline
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Opcode & Mnemonic & Operand 1 & Operand 2 \\
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\hline\hline
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0x60 & sub & Register & Register \\
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\hline
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\end{tabular}\\[6pt]
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Performs subtraction on a register with a value from another (or the same) register.
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\OpcodeTable{0x20}{sub}{Register}{Register}\\[6pt]
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Performs subtraction on a register with a value from another (or the same) register.
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\section{JMP (Jump)}
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\begin{tabular}{ c c c c }
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\hline
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Opcode & Mnemonic & Operand 1 & Operand 2 \\
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\hline\hline
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0x60 & jmp & Address & None \\
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\hline
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\end{tabular}
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Jumps unconditionally to a memory address.
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\OpcodeTable{0x20}{jmp}{Address}{None}\\[6pt]
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Jumps unconditionally to a memory address.
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\section{JZ (Jump if Zero)}
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\begin{tabular}{ c c c c }
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\hline
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Opcode & Mnemonic & Operand 1 & Operand 2 \\
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\hline\hline
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0x60 & jz & Address & None \\
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\hline
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\end{tabular}
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Jumps to a memory address if some register is zero.
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\OpcodeTable{0x20}{jz}{Register}{None}\\[6pt]
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Jumps to a memory address if some register is zero.
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\section{JG (Jump if Greater Than)}
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\OpcodeTable{0x70}{jg}{Address}{None}\\[6pt]
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Jump to the Address if some register is greater than zero.
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\section{JL (Jump if Less Than)}
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\section{AND (Logical AND)}
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\section{XOR (Logical Exclusive OR)}
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@@ -140,5 +104,7 @@
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\section{NOT (Logical Negation)}
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\section{SHR (Shift Right)}
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\section{SHL (Shift Left)}
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\section{INC (Increment)}
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\section{DEC (Decrement)}
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\end{document}
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