Updated the ISA and added links in the table of contents.
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@@ -1,5 +1,9 @@
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\documentclass[a4paper,12pt]{book}
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\usepackage{tikz}
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\usepackage{hyperref}
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\hypersetup{
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linktoc=all
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}
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\title{Unnamed Machine}
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\author{A Very Terrible 16-bit Machine}
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@@ -27,6 +31,7 @@
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\item[] ...
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\item[] R8
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\end{itemize}
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Additionally, there will be a special status register that will be a signed 16 bit register that the compare and jump instructions will read or write to when determining what action, if any, they'll take.
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\section{Memory Model}
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Memory will be implicitly mapped I/O. The bottom 3201 bytes of memory will be reserved for the keyboard input and graphics.
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A single byte is reserved for the keyboard's input. The current key will be stored in byte 0xF37E, with the most significant bit being a flag indicating that the keyboard
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@@ -50,7 +55,8 @@
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\section{Instruction Encoding}
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Instructions are fixed to exactly one byte (8 bits).
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Instructions that work with two operands the register for operand one will be encoded in the three least significant bits. So an instruction with format XXXX X000 will use Register 1 and so forth all the way to XXXX X111, which will be Register 8.
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\begin{figure}
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%https://tex.stackexchange.com/questions/32598/force-latex-image-to-appear-in-the-section-in-which-its-declared
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\begin{figure}[!htb]
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\centering
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\begin{tabular}{ c c }
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\hline
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@@ -86,10 +92,10 @@
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Loads an immediate machine word into the register clearing the high nibble if the value is less then 256.
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\section{CMP (Compare)}
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\OpcodeTable{0x20}{cmp}{Register}{Register}\\[6pt]
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Compares two registers and somewhere sets a result, maybe in register 1?
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Compares two registers and somewhere sets a result in the status register.
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\section{CMPI (Compare Immediate)}
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\OpcodeTable{0x00}{cmpi}{Register}{Constant}\\[6pt]
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Compares an immediate 2 byte value to the contents of a register setting a result.
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Compares an immediate 2 byte value to the contents of a register setting the status register accordingly.
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\section{ADD (Add)}
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\OpcodeTable{0x20}{add}{Register}{Register}\\[6pt]
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Performs addition on a register with a value from another (or the same) register.
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@@ -101,20 +107,38 @@
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Jumps unconditionally to a memory address.
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\section{JZ (Jump if Zero)}
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\OpcodeTable{0x20}{jz}{Register}{None}\\[6pt]
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Jumps to a memory address if some register is zero.
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Jumps to a memory address if the status flag is zero.
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\section{JG (Jump if Greater Than)}
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\OpcodeTable{0x70}{jg}{Address}{None}\\[6pt]
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Jump to the Address if some register is greater than zero.
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Jump to the Address if the status flag is greater than zero.
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\section{JL (Jump if Less Than)}
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\OpcodeTable{0x00}{jl}{Address}{None}\\[6pt]
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Jumps to the address if the status flag is less than zero.
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\section{AND (Logical AND)}
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\OpcodeTable{0x00}{and}{Register}{Register}\\[6pt]
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Logical ANDs the two registers together storing the result in operand 1.
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\section{XOR (Logical Exclusive OR)}
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\OpcodeTable{0x00}{xor}{Register}{Register}\\[6pt]
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Logical XORs the two registers together storing the result in operand 1.
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\section{OR (Logical OR)}
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\OpcodeTable{0x00}{or}{Register}{Register}\\[6pt]
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Logical ORs the two registers together storing the result in operand 1.
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\section{NOT (Logical Negation)}
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\OpcodeTable{0x00}{not}{Register}{None}\\[6pt]
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Inverts the bits of the target register.
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\section{SHR (Shift Right)}
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\OpcodeTable{0x00}{shr}{Register}{Constant}\\[6pt]
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Bit-wise shifts the contents of the register right Constant number of times.
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\section{SHL (Shift Left)}
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\OpcodeTable{0x00}{shl}{Register}{Constant}\\[6pt]
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Bit-wise shifts the contents of the register left Constant number of times.
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\section{INC (Increment)}
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\OpcodeTable{0x00}{inc}{Register}{None}
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\OpcodeTable{0x00}{inc}{Register}{None}\\[6pt]
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Increments the contents of the register by one. Over-flows will not be reported.
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\section{DEC (Decrement)}
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\OpcodeTable{0x00}{dec}{Register}{None}
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\OpcodeTable{0x00}{dec}{Register}{None}\\[6pt]
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Decrements the contents of the register by one. Under-flows will not be reported.
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\section{NOP (No Operation)}
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\OpcodeTable{0x00}{nop}{None}{None}\\[6pt]
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Skips a clock cycle, incrementing the program counter by one.
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\end{document}
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