Updated the way I build the opcode table to be a little less repetitive. Now instead of making it an environment it is now a command that will build the arguments based on the 'Options' bit hexcode.

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2025-02-24 01:14:30 -06:00
parent 5068c6c293
commit 02b3c9185d
+72 -43
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@@ -1,22 +1,71 @@
% When the argument list ends with "b" that makes the body of the environment an argument.
% To quote section 3.6 Body of an environment:
% The approach taken in xparse is different from the earlier packages environ or newenviron: the body of
% the environment is provided to the code part as a usual argument #1, #2 etc., rather than
% stored in a macro such as \BODY.
% Source: https://mirrors.rit.edu/CTAN/macros/latex/contrib/l3packages/xparse.pdf (Released 2024-08-16)
\NewDocumentEnvironment{opcodetable}{ m m b } {
\begin{tabularx}{\textwidth}{ | c | X | c | c | }
\hline
Opcode & Instruction & Operand One & Operand Two \\
\hline
#3
\hline
\end{tabularx}
\paragraph{Description} #1
\paragraph{Flags Affected} #2
}{
\ExplSyntaxOn
% Opcode, Opcode Name, Description, Flags Affected, Options
\NewDocumentCommand{\createoptable}{ m m m m m }{
%\newcommand{\row}[3] {#1~#3 & #2 & Temp & \cs_if_eq:NNTF {#3} {E} { Allowed} { None } \\ \hline}
%\clist_new:N \l_options
%\clist_set:Nn \l_options {#3}
%\begin{tabularx}{\textwidth}{ | c | }
% \clist_map_inline:Nn \l_options { ##1 \\ }
%\end{tabularx}
%\seq_set_split:Nnn \l_tmpa_seq {,} {#3}
\clist_clear_new:N \l_options
\clist_set:Nn \l_options {#3}
\seq_clear:N \l_tmpa_seq
\tl_set:Nn \l_tmpa_seq { \begin{tabularx}{\textwidth}{ | c | X | c | c | } \hline }
\tl_put_right:Nn \l_tmpa_seq { Opcode & Instruction & Operand One & Operand Two \\ \hline }
\clist_map_inline:Nn \l_options {
%\tl_put_right:Nn \l_tmpa_seq { #1~##1 & #2 & Temp & \cs_if_eq:NNTF {##1} {E} { Allowed} { None } \\ \hline }
\str_case:nnF{##1} {
{1} {
\tl_put_right:Nn \l_tmpa_seq { #1 & #2 /r, /r1 & r & r1 \\ \hline }
}{2}{
\tl_put_right:Nn \l_tmpa_seq { #1 & #2 /r, /r2 & r & r2 \\ \hline }
}{3}{
\tl_put_right:Nn \l_tmpa_seq { #1 & #2 /r, /r3 & r & r2 \\ \hline }
}{4}{
\tl_put_right:Nn \l_tmpa_seq { #1 & #2 /r, /r4 & r & r2 \\ \hline }
}{5}{
\tl_put_right:Nn \l_tmpa_seq { #1 & #2 /r, /r5 & r & r2 \\ \hline }
}{D}{
\tl_put_right:Nn \l_tmpa_seq { #1 & #2 /r, /rD & r & r2 \\ \hline }
}{E}{
\tl_put_right:Nn \l_tmpa_seq { #1 & #2 /r, /rE & r & r2 \\ \hline }
}{F}{
\tl_put_right:Nn \l_tmpa_seq { #1 & #2 /r, /rF & r & r2 \\ \hline }
}
}{ FALSE }
%\tl_put_right:Ne \l_tmpa_seq { \my_parse #1 #2 #3 }
}
\tl_put_right:Nn \l_tmpa_seq { \end{tabularx} }
\tl_put_right:Nn \l_tmpa_seq { \paragraph{Description} #5 }
\tl_put_right:Nn \l_tmpa_seq { \paragraph{Flags Affected} #4 }
\tl_use:N \l_tmpa_seq
%\begin{tabularx}{\textwidth}{ | c | X | c | c | } \hline
%Opcode & Instruction & Operand One & Operand Two \\ \hline
%\clist_map_inline:Nn \l_options { #1~##1 \parseoption{#2}{##1} \\ \hline } %{ \row{#1}{##1}{#2} }
%\l_parse_row:nn{#1}{#2}
%\end{tabularx}
%\paragraph{Description} #5
%\paragraph{Flags Affected} #4
}
\ExplSyntaxOff
\chapter{Instruction Set Architecture}
In general instructions are variable length depending on the number of arguments and their width. The first byte of an instruction is the \textit{opcode} which tells the machine what operation is to be performed. If one or more arguments are required, then the next byte is the \textit{options} byte which describes the type and width of the argument(s). The exact meaning of all the bits in the \textit{options} byte are shown in Figure \ref{fig:opencoding}. The order of the arguments follows the AT\&T syntax, meaning the left hand argument is the \textit{source} and the right hand argument is the \textit{destination}.
@@ -105,35 +154,15 @@ In general instructions are variable length depending on the number of arguments
\section{Instructions}
The /r represents a byte that specifies a register. /immX is for the immediate data type, where \textit{X} defines the width, which are 8, 16, or 32 bits. An address is defined as /addrX with the \textit{X} denoting the size of the data that will be written which can be 8, 16 or 32 bits, with the address itself always being 32-bits wide.
\subsection{Add}
\begin{opcodetable}
{
\createoptable{01}{add}{1, 2, 3}{ OF and ZF. }
{
Adds two unsigned values together, the source (operand one) and the destination (operand two), storing the result in destination. The overflow flag (OF) is set if the result is less than the source and the zero flag (ZF) is set when the result of addition is zero.
}
{
OF and ZF.
}
01 \rRArgH\byteWidthH & add byte /r, /r & /r & /r \\
01 \rRArgH\shortWidthH & add short /r, /r & /r & /r \\
01 \rRArgH\intWidthH & add (int) /r, /r & /r & /r \\
01 \immRArgH\byteWidthH & add byte /imm8, /r & /imm8 & /r \\
01 \immRArgH\shortWidthH & add short /imm16, /r & /imm16 & /r \\
01 \immRArgH\intWidthH & add (int) /imm32, /r & /imm32 & /r \\
\end{opcodetable}
\subsection{Sub}
\begin{tabularx}{\textwidth}{ | c | X | c | c | }
\hline
Opcode & Instruction & Operand One & Operand Two \\
\hline
02 \rRArgH\byteWidthH & sub byte /r, /r & /r & /r \\
02 \rRArgH\shortWidthH & sub short /r, /r & /r & /r \\
02 \rRArgH\intWidthH & sub (int) /r, /r & /r & /r \\
02 \immRArgH\byteWidthH & sub byte /imm8, /r & /imm8 & /r \\
02 \immRArgH\shortWidthH & sub short /imm16, /r & /imm16 & /r \\
02 \immRArgH\intWidthH & sub (int) /imm32, /r & /imm32 & /r \\
\hline
\end{tabularx}
\paragraph{Description} Subtracts two unsigned values, the source (operand one) and the destination (operand two), storing the result in destination. The underflow flag (UF) is set if the result is greater than the source and the zero flag (ZF) is set when the result of subtraction is zero.
\paragraph{Flags Affected} UF and ZF.
\createoptable{02}{sub}{F, E, D}{ UF and ZF. }
{
Subtracts two unsigned values, the source (operand one) and the destination (operand two), storing the result in destination. The underflow flag (UF) is set if the result is greater than the source and the zero flag (ZF) is set when the result of subtraction is zero.
}
\subsection{Mul}
\begin{tabularx}{\textwidth}{ | c | X | c | c | }
\hline