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@@ -53,20 +53,39 @@
 	\end{figure}
 	\chapter{Instruction Set Architecture}
 	\section{Instruction Encoding}
-	Instructions are fixed to exactly one byte (8 bits).
-	Instructions that work with two operands the register for operand one will be encoded in the three least significant bits. So an instruction with format XXXX X000 will use Register 1 and so forth all the way to XXXX X111, which will be Register 8.
-	%https://tex.stackexchange.com/questions/32598/force-latex-image-to-appear-in-the-section-in-which-its-declared
+	The instruction encoding is fixed width to exactly 8 bites wide.
+	The encoding for the instructions will differ depending on if the opcode requires a register as its first operand.
+	For instructions that require, as their first argument, a register the encoding format will be as shown in Figure \ref{fig:WithRegister}.
+	The lower 3 bits may be any bit pattern as long as at least one bit is set in the upper 5 bits.
+	%https://tex.stackexchange.com/questions/32598/force-latex-image-to-appear-in-the-section-in-which-its-declared	
 	\begin{figure}[!htb]
 		\centering
 		\begin{tabular}{ c c }
-			\hline
 			Instruction & Register \\
-			\hline\hline
-			0000 0 & 000 \\
+			\hline
+			XXXX X & 000 \\
 			\hline
 		\end{tabular}
-		\caption{Encoding Layout}
+		\caption{Encoding Layout, Register Required}
+		\label{fig:WithRegister}
 	\end{figure}
+
+	Figure \ref{fig:NoRegisterEncoding} shows how encoding will look for instructions that lack arguments or do not require a register.
+	In contrast with the previous encoding scheme the upper 5 bits MUST be zero, allowing 7 possible instructions to use this format.
+	All zeroes is not considered a legal instruction.
+
+	\begin{figure}[!htb]
+	\centering
+	\begin{tabular}{ c c }
+		Must Be Zero & Instruction \\
+		\hline
+		0000 0 & XXX \\
+		\hline
+	\end{tabular}
+	\caption{Encoding Layout, Register Required}
+	\label{fig:NoRegisterEncoding}
+\end{figure}
+	
 	\section{Notes}
 	For the opcodes that load or store data at the assembly language level we could have the mnemonics
 	"store" and "load" and have the assembler pick the opcode based on the inclusion of the word "byte"