I believe I have the bit patterns for my opcodes worked out.

src/opcodes.c

@@ -17,31 +17,39 @@ Instruction instructions[OPCODECOUNT] = {
 };
 
 /*
-    NOP  - 0000 0000
+    NOP  - 0000 0000 NOP
     JZ   - 0000 0001 JZ Address
     INT  - 0000 0010 INT Constant
     YLD  - 0000 0011 YLD
     RET  - 0000 0100 RET
     CALL - 0000 0101 CALL Address
-    //IN reads from a port number specified by either a register or a constant.
-    IN   - 0000 0110 IN Constant
-         - 0000 0111 IN REG
-    COPY - 0000 1XXX COPY REG, REG
-         - 0001 0XXX COPY REG, Constant    
-         - 0010 0XXX COPY REG, Address
-         - 0010 1XXX COPY Address, REG
-         - 0011 0XXX COPY Address, Constant
-         - 0011 1XXX COPY Address, Address
+    JMP  - 0000 0110 JMP Address
+
+    COPY - 0010 0XXX COPY REG, REG
+         - 0010 1XXX COPY REG, Constant    
+         - 0011 0XXX COPY REG, Address
+         - 0010 0XXX COPY Address, REG
+         - 0010 1XXX COPY Address, Constant
+         - 0011 0XXX COPY Address, Address
+
     ADD  - 0100 0XXX ADD REG, REG
          - 0100 1XXX ADD REG, Constant
-    SUB  - 0101 0XXX SUB REG, REG
-         - 0101 1XXX SUB REG, Constant
-    CMP  - 0110 0XXX CMP REG, REG
-         - 0110 1XXX CMP REG, Constant
-         - 0111 0XXX CMP REG, Address
-    OUT  - 0111 1XXX OUT REG
-    JMP  - 1000 0000 JMP Address
+    SUB  - 0110 0XXX SUB REG, REG
+         - 0110 1XXX SUB REG, Constant
+    CMP  - 1000 0XXX CMP REG, REG
+         - 1000 1XXX CMP REG, Constant
+         - 1001 0XXX CMP REG, Address
+
+    OUT  - 1111 1XXX OUT REG
 */
+//COPY      001X XXXX
+//ADD       010X XXXX
+//SUB       011X XXXX
+//CMP       100X XXXX
+//REG       XXX0 0XXX
+//Constant  XXX0 1XXX
+//Address   XXX1 0XXX
+//R1        XXXX X001 -> XXXX X111 (R1 to R8)
 
 Register registers[REGISTERCOUNT] = {
     { "r1", R1 },