From 925f7703d6efcfb941e969c18713ae4f9960d397 Mon Sep 17 00:00:00 2001 From: Garritt McCune Date: Thu, 22 Sep 2022 20:49:20 +0000 Subject: [PATCH] Updated the ISA, hopefully I can get this all put together in a thought out way. --- docs/document.tex | 109 ++++++++++++++++++++++++++++++++++------------ 1 file changed, 81 insertions(+), 28 deletions(-) diff --git a/docs/document.tex b/docs/document.tex index a56f919..8a0a859 100644 --- a/docs/document.tex +++ b/docs/document.tex @@ -9,7 +9,7 @@ \tableofcontents \chapter{Overview} \section{Introduction} - This is a very poorly thought out 16-bit machine, but you've got to start somewhere. Currently debating between a CPU status register, 80x86 style, or just placing arithmetic results into a predetermined register. + This is a very poorly thought out 16-bit machine, but you've got to start somewhere. Currently debating between a CPU status register, 80x86 style, or just placing arithmetic results into a predetermined register. This is more of a load–store architecture to try and keep the instruction set simple. \section{Registers} The following are the general purpose registers that can be used. \begin{itemize} @@ -36,56 +36,109 @@ \end{tikzpicture} \caption{Memory Layout} \end{figure} - \chapter{ISA} + \chapter{Instruction Set Architecture} \section{Instruction Encoding} - Instructions are fixed to one byte in length. For instructions that can take a register as their first or second operand the 3 least significant bits are set - to indicate the register file to use. So an instruction with format XXXX X000 will use Register 1 and so forth all the way to the pattern XXXX X111, which will be Register 8. - In instances where the second operand may be one of three options bits 4 and 5 are set as shown below:\\\\ - \begin{tabular}{ c c } - \hline - Bit Pattern & Type \\ - \hline - XXX0 0XXX & Register \\ - XXX0 1XXX & Constant \\ - XXX1 0XXX & Address \\ - \hline - \end{tabular} - \section{COPY} + Instructions are fixed to exactly one byte (8 bits). + Instructions that work with two operands the register for operand one will be encoded in the three least significant bits. So an instruction with format XXXX X000 will use Register 1 and so forth all the way to the pattern XXXX X111, which will be Register 8. + \begin{figure} + \centering + \begin{tabular}{ c c } + \hline + Instruction & Register \\ + \hline\hline + 0000 0 & 000 \\ + \hline + \end{tabular} + \caption{Encoding Layout} + \end{figure} + \section{STOB (Store Byte)} \begin{tabular}{ c c c c } \hline Opcode & Mnemonic & Operand 1 & Operand 2 \\ \hline\hline - 0x20 & COPY & Register & Immediate 16 / Address, Register \\ - 0xA0 & COPY & Address & Immediate 16 / Address, Register \\ + 0x20 & stob & Register & Memory Address \\ \hline \end{tabular}\\[6pt] - Copies 2 bytes of data from either a memory address, a runtime constant or a CPU register into either another CPU register or a memory location. - \section{CMP} + Stores a single byte (the lower nibble) from a register to a memory address. + \section{STOW (Store Machine Word)} \begin{tabular}{ c c c c } \hline Opcode & Mnemonic & Operand 1 & Operand 2 \\ \hline\hline - 0x80 & CMP & Register & Register, Immediate 16 / Address \\ + 0x20 & stow & Register & Memory Address \\ \hline \end{tabular}\\[6pt] - Compares two values and sets a CPU status flag (maybe...). - \section{ADD} + Stores a machine word from a register to a memory address. + \section{LODB (Load Byte)} + \begin{tabular}{ c c c c } + \hline + Opcode & Mnemonic & Operand 1 & Operand 2 \\ + \hline\hline + 0x20 & lodb & Register & Address \\ + \hline + \end{tabular}\\[6pt] + Loads a single byte into a register from a memory address. + \section{LODW (Load Machine Word)} + \begin{tabular}{ c c c c } + \hline + Opcode & Mnemonic & Operand 1 & Operand 2 \\ + \hline\hline + 0x20 & lodw & Register & Address \\ + \hline + \end{tabular}\\[6pt] + Loads a word into a register from a memory address. + \section{CMP (Compare)} + \begin{tabular}{ c c c c } + \hline + Opcode & Mnemonic & Operand 1 & Operand 2 \\ + \hline\hline + 0x80 & cmp & Register & Register \\ + \hline + \end{tabular}\\[6pt] + Compares two registers and somewhere sets a result, maybe in register 1? + \section{ADD (Add)} \begin{tabular}{ c c c c } \hline Opcode & Mnemonic & Operand 1 & Operand 2 \\ \hline\hline - 0x40 & ADD & Register & Register, Immediate 16 \\ + 0x40 & add & Register & Register \\ \hline \end{tabular}\\[6pt] - Performs addition on a register with a value from another (or the same) register or a runtime constant. - \section{SUB} + Performs addition on a register with a value from another (or the same) register. + \section{SUB (Subtract)} \begin{tabular}{ c c c c } \hline Opcode & Mnemonic & Operand 1 & Operand 2 \\ \hline\hline - 0x60 & SUB & Register & Register, Immediate 16 \\ + 0x60 & sub & Register & Register \\ \hline \end{tabular}\\[6pt] - Performs subtraction on a register with a value from another (or the same) register or a runtime constant. - + Performs subtraction on a register with a value from another (or the same) register. + \section{JMP (Jump)} + \begin{tabular}{ c c c c } + \hline + Opcode & Mnemonic & Operand 1 & Operand 2 \\ + \hline\hline + 0x60 & jmp & Address & None \\ + \hline + \end{tabular} + Jumps unconditionally to a memory address. + \section{JZ (Jump if Zero)} + \begin{tabular}{ c c c c } + \hline + Opcode & Mnemonic & Operand 1 & Operand 2 \\ + \hline\hline + 0x60 & jz & Address & None \\ + \hline + \end{tabular} + Jumps to a memory address if some register is zero. + \section{JG (Jump if Greater Than)} + \section{JL (Jump if Less Than)} + \section{AND (Logical AND)} + \section{XOR (Logical Exclusive OR)} + \section{OR (Logical OR)} + \section{NOT (Logical Negation)} + \section{SHR (Shift Right)} + \section{SHL (Shift Left)} + \end{document}